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3227166c3b
The DPAUX code paths already configure the pads in AUX mode, but there is no way to reconfigure them in I2C mode for HDMI (the DPAUX module is unused in that case). Enabling the pads in I2C mode by default is the quickest way to support HDMI. Eventually this may need an explicit call in the user drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/*
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* Copyright (C) 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DRM_TEGRA_DPAUX_H
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#define DRM_TEGRA_DPAUX_H
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#define DPAUX_CTXSW 0x00
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#define DPAUX_INTR_EN_AUX 0x01
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#define DPAUX_INTR_AUX 0x05
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#define DPAUX_INTR_AUX_DONE (1 << 3)
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#define DPAUX_INTR_IRQ_EVENT (1 << 2)
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#define DPAUX_INTR_UNPLUG_EVENT (1 << 1)
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#define DPAUX_INTR_PLUG_EVENT (1 << 0)
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#define DPAUX_DP_AUXDATA_WRITE(x) (0x09 + ((x) << 2))
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#define DPAUX_DP_AUXDATA_READ(x) (0x19 + ((x) << 2))
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#define DPAUX_DP_AUXADDR 0x29
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#define DPAUX_DP_AUXCTL 0x2d
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#define DPAUX_DP_AUXCTL_TRANSACTREQ (1 << 16)
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#define DPAUX_DP_AUXCTL_CMD_AUX_RD (9 << 12)
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#define DPAUX_DP_AUXCTL_CMD_AUX_WR (8 << 12)
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#define DPAUX_DP_AUXCTL_CMD_MOT_RQ (6 << 12)
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#define DPAUX_DP_AUXCTL_CMD_MOT_RD (5 << 12)
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#define DPAUX_DP_AUXCTL_CMD_MOT_WR (4 << 12)
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#define DPAUX_DP_AUXCTL_CMD_I2C_RQ (2 << 12)
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#define DPAUX_DP_AUXCTL_CMD_I2C_RD (1 << 12)
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#define DPAUX_DP_AUXCTL_CMD_I2C_WR (0 << 12)
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#define DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY (1 << 8)
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#define DPAUX_DP_AUXCTL_CMDLEN(x) ((x) & 0xff)
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#define DPAUX_DP_AUXSTAT 0x31
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#define DPAUX_DP_AUXSTAT_HPD_STATUS (1 << 28)
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#define DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK (0xf0000)
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#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR (1 << 11)
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#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR (1 << 10)
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#define DPAUX_DP_AUXSTAT_RX_ERROR (1 << 9)
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#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR (1 << 8)
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#define DPAUX_DP_AUXSTAT_REPLY_MASK (0xff)
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#define DPAUX_DP_AUX_SINKSTAT_LO 0x35
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#define DPAUX_DP_AUX_SINKSTAT_HI 0x39
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#define DPAUX_HPD_CONFIG 0x3d
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#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME(x) (((x) & 0xffff) << 16)
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#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME(x) ((x) & 0xffff)
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#define DPAUX_HPD_IRQ_CONFIG 0x41
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#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME(x) ((x) & 0xffff)
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#define DPAUX_DP_AUX_CONFIG 0x45
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#define DPAUX_HYBRID_PADCTL 0x49
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#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV (1 << 15)
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#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV (1 << 14)
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#define DPAUX_HYBRID_PADCTL_AUX_CMH(x) (((x) & 0x3) << 12)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVZ(x) (((x) & 0x7) << 8)
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#define DPAUX_HYBRID_PADCTL_AUX_DRVI(x) (((x) & 0x3f) << 2)
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#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV (1 << 1)
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#define DPAUX_HYBRID_PADCTL_MODE_I2C (1 << 0)
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#define DPAUX_HYBRID_PADCTL_MODE_AUX (0 << 0)
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#define DPAUX_HYBRID_SPARE 0x4d
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#define DPAUX_HYBRID_SPARE_PAD_POWER_DOWN (1 << 0)
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#define DPAUX_SCRATCH_REG0 0x51
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#define DPAUX_SCRATCH_REG1 0x55
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#define DPAUX_SCRATCH_REG2 0x59
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#endif
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