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To allow multiple platforms to use the PXA27x OHCI driver, the platform code needs to be moved into the board specific files in arch/arm/mach-pxa. This patch does this for mainstone and adds preliminary hooks to allow other boards to use the driver. This has been compile tested for mainstone and successfully run on Spitz (Sharp Zaurus SL-C3000) with the addition of an appropriate board support file. Signed-off-by: Richard Purdie <rpurdie@rpsys.net> Signed-off-by: Nicolas Pitre <nico@cam.org> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
213 lines
4.6 KiB
C
213 lines
4.6 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa27x.c
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*
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* Author: Nicolas Pitre
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* Created: Nov 05, 2002
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* Copyright: MontaVista Software Inc.
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*
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* Code specific to PXA27x aka Bulverde.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/ohci.h>
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#include "generic.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int get_clk_frequency_khz( int info)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M, n2, N, S;
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int cccr_a, t, ht, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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t = clkcfg & (1 << 1);
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ht = clkcfg & (1 << 2);
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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n2 = (ccsr>>7) & 0xf;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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N = (L * n2) / 2;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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S = (b) ? L : (L/2);
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if (info) {
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
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(t) ? "" : "in" );
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printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
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S / 1000000, (S % 1000000) / 10000 );
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}
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return (t) ? (N/1000) : (L/1000);
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}
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/*
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* Return the current mem clock frequency in units of 10kHz as
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* reflected by CCCR[A], B, and L
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*/
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unsigned int get_memclk_frequency_10khz(void)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M;
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int cccr_a, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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return (M / 10000);
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}
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/*
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* Return the current LCD clock frequency in units of 10kHz as
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*/
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unsigned int get_lcdclk_frequency_10khz(void)
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{
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unsigned long ccsr;
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unsigned int l, L, k, K;
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ccsr = CCSR;
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l = ccsr & 0x1f;
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k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
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L = l * BASE_CLK;
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K = L / k;
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return (K / 10000);
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}
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EXPORT_SYMBOL(get_clk_frequency_khz);
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EXPORT_SYMBOL(get_memclk_frequency_10khz);
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EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
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#ifdef CONFIG_PM
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int pxa_cpu_pm_prepare(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_MEM:
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case PM_SUSPEND_STANDBY:
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return 0;
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default:
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return -EINVAL;
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}
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}
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void pxa_cpu_pm_enter(suspend_state_t state)
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{
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extern void pxa_cpu_standby(void);
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extern void pxa_cpu_suspend(unsigned int);
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extern void pxa_cpu_resume(void);
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if (state == PM_SUSPEND_STANDBY)
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CKEN = CKEN22_MEMC | CKEN9_OSTIMER | CKEN16_LCD |CKEN0_PWM0;
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else
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CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
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/* ensure voltage-change sequencer not initiated, which hangs */
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PCFR &= ~PCFR_FVC;
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/* Clear edge-detect status register. */
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PEDR = 0xDF12FE1B;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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pxa_cpu_standby();
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break;
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa_cpu_suspend(PWRMODE_SLEEP);
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break;
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}
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}
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#endif
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/*
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* device registration specific to PXA27x.
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*/
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static u64 pxa27x_dmamask = 0xffffffffUL;
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static struct resource pxa27x_ohci_resources[] = {
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[0] = {
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.start = 0x4C000000,
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.end = 0x4C00ff6f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_USBH1,
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.end = IRQ_USBH1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ohci_device = {
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.name = "pxa27x-ohci",
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.id = -1,
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.dev = {
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.dma_mask = &pxa27x_dmamask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
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.resource = pxa27x_ohci_resources,
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};
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void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
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{
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ohci_device.dev.platform_data = info;
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}
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static struct platform_device *devices[] __initdata = {
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&ohci_device,
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};
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static int __init pxa27x_init(void)
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{
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return platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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subsys_initcall(pxa27x_init);
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