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These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM Conflicts: * In Kconfig.debug, various additions trivially conflict, the list should be kept in alphabetical order when resolving. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUdLnl2CrR//JCVInAQIrKhAAwvtsGNe6j9nDuLEitWtQAmhHYZQyUJ8k o9j/1j1CqhE8C0bLRud8D4m1GxfxbGeRm2d0HoNbxda3FmntUufqBDi6neMiQiLO VltC5rOYL8Mday0Asc3SBfjBj8SZC2bypicKy5zUfzsObCBt343g1WvYffMDNmwH FveOQK6q2BKmO67cazc9tk5xmxjVwP/LB8r5mQtiXmMguw0R+ZIDDIP6xaURFkxX SAElleD2wtvpVHP1d6AKHpXN99u3xV3uoJjKljECEXdBzW/ZX8m7FG2tKY5xy368 ta0Nhh2MSRnBhUYOH9uah4PQWYEsbZ+M/W+3J9tKRu6q9D/c/AAxILyXUY2tcHNC o1UwcUn1druirx3X1AW8HYAGNwW7BD3HANzIiUkQZG7ByfM4qCtUEo2SAFNIGBoR v1FMLhMPgMWotZnKrDQQd0anxkKIOFaSMRVgpQLW2jQt/B7sHLmEH2yDffkbSD76 PQDThnW/dfm9dgeK+X4fPrveIMKbjQlbFz0okN+LPsUf8e1045HBgCi2A0lTIGWM kVVgXHKKXi8G8HBa4VyDlORVHXk1bJEheF+zlDvdk4fHkcf+H/OfvFG2O9TdIdpb ITXRyyteaRM4YIZpnJbzeeZDZXT89c2ah7xq36iM+L1ScidyntPquViXeasSc8r6 pKu9ZDc0Mow= =cRu2 -----END PGP SIGNATURE----- Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late changes from Arnd Bergmann: "These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) ARM: ux500: bail out on alien cpus ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins serial: sh-sci: Initialise variables before access in sci_set_termios() ARM: stih41x: Add B2020 board support ARM: stih41x: Add B2000 board support ARM: sti: Add DEBUG_LL console support ARM: sti: Add STiH416 SOC support ARM: sti: Add STiH415 SOC support ARM: msm: Migrate to common clock framework ARM: msm: Make proc_comm clock control into a platform driver ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver ARM: msm: Remove clock-7x30.h include file ARM: msm: Remove custom clk_set_{max,min}_rate() API ARM: msm: Remove custom clk_set_flags() API msm: iommu: Use clk_set_rate() instead of clk_set_min_rate() msm: iommu: Convert to clk_prepare/unprepare msm_sdcc: Convert to clk_prepare/unprepare usb: otg: msm: Convert to clk_prepare/unprepare msm_serial: Use devm_clk_get() and properly return errors msm_serial: Convert to clk_prepare/unprepare ...
318 lines
11 KiB
Plaintext
318 lines
11 KiB
Plaintext
Samsung GPIO and Pin Mux/Config controller
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Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
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controller. It controls the input/output settings on the available pads/pins
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and also provides ability to multiplex and configure the output of various
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on-chip controllers onto these pads.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
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- "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
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- "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
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- "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
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- "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
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- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
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- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
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- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
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- reg: Base address of the pin controller hardware module and length of
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the address space it occupies.
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- Pin banks as child nodes: Pin banks of the controller are represented by child
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nodes of the controller node. Bank name is taken from name of the node. Each
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bank node must contain following properties:
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- gpio-controller: identifies the node as a gpio controller and pin bank.
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- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
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binding is used, the amount of cells must be specified as 2. See the below
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mentioned gpio binding representation for description of particular cells.
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Eg: <&gpx2 6 0>
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<[phandle of the gpio controller node]
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[pin number within the gpio controller]
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[flags]>
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Values for gpio specifier:
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- Pin number: is a value between 0 to 7.
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- Flags: 0 - Active High
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1 - Active Low
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- Pin mux/config groups as child nodes: The pin mux (selecting pin function
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mode) and pin config (pull up/down, driver strength) settings are represented
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as child nodes of the pin-controller node. There should be atleast one
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child node and there is no limit on the count of these child nodes.
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The child node should contain a list of pin(s) on which a particular pin
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function selection or pin configuration (or both) have to applied. This
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list of pins is specified using the property name "samsung,pins". There
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should be atleast one pin specfied for this property and there is no upper
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limit on the count of pins that can be specified. The pins are specified
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using pin names which are derived from the hardware manual of the SoC. As
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an example, the pins in GPA0 bank of the pin controller can be represented
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as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
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The format of the pin names should be (as per the hardware manual)
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"[pin bank name]-[pin number within the bank]".
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The pin function selection that should be applied on the pins listed in the
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child node is specified using the "samsung,pin-function" property. The value
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of this property that should be applied to each of the pins listed in the
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"samsung,pins" property should be picked from the hardware manual of the SoC
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for the specified pin group. This property is optional in the child node if
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no specific function selection is desired for the pins listed in the child
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node. The value of this property is used as-is to program the pin-controller
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function selector register of the pin-bank.
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The child node can also optionally specify one or more of the pin
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configuration that should be applied on all the pins listed in the
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"samsung,pins" property of the child node. The following pin configuration
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properties are supported.
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- samsung,pin-pud: Pull up/down configuration.
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- samsung,pin-drv: Drive strength configuration.
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- samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
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- samsung,pin-drv-pdn: Drive strength configuration in power down mode.
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The values specified by these config properties should be derived from the
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hardware manual and these values are programmed as-is into the pin
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pull up/down and driver strength register of the pin-controller.
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Note: A child should include atleast a pin function selection property or
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pin configuration property (one or more) or both.
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The client nodes that require a particular pin function selection and/or
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pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
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file.
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External GPIO and Wakeup Interrupts:
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The controller supports two types of external interrupts over gpio. The first
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is the external gpio interrupt and second is the external wakeup interrupts.
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The difference between the two is that the external wakeup interrupts can be
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used as system wakeup events.
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A. External GPIO Interrupts: For supporting external gpio interrupts, the
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following properties should be specified in the pin-controller device node.
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- interrupt-parent: phandle of the interrupt parent to which the external
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GPIO interrupts are forwarded to.
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- interrupts: interrupt specifier for the controller. The format and value of
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the interrupt specifier depends on the interrupt parent for the controller.
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In addition, following properties must be present in node of every bank
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of pins supporting GPIO interrupts:
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- interrupt-controller: identifies the controller node as interrupt-parent.
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- #interrupt-cells: the value of this property should be 2.
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- First Cell: represents the external gpio interrupt number local to the
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external gpio interrupt space of the controller.
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- Second Cell: flags to identify the type of the interrupt
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- 1 = rising edge triggered
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- 2 = falling edge triggered
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- 3 = rising and falling edge triggered
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- 4 = high level triggered
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- 8 = low level triggered
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B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
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child node representing the external wakeup interrupt controller should be
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included in the pin-controller device node. This child node should include
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the following properties.
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- compatible: identifies the type of the external wakeup interrupt controller
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The possible values are:
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- samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller
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found on Samsung S3C24xx SoCs except S3C2412 and S3C2413,
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- samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller
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found on Samsung S3C2412 and S3C2413 SoCs,
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- samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
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found on Samsung S3C64xx SoCs,
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- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
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found on Samsung Exynos4210 SoC.
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- interrupt-parent: phandle of the interrupt parent to which the external
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wakeup interrupts are forwarded to.
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- interrupts: interrupt used by multiplexed wakeup interrupts.
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In addition, following properties must be present in node of every bank
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of pins supporting wake-up interrupts:
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- interrupt-controller: identifies the node as interrupt-parent.
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- #interrupt-cells: the value of this property should be 2
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- First Cell: represents the external wakeup interrupt number local to
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the external wakeup interrupt space of the controller.
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- Second Cell: flags to identify the type of the interrupt
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- 1 = rising edge triggered
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- 2 = falling edge triggered
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- 3 = rising and falling edge triggered
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- 4 = high level triggered
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- 8 = low level triggered
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Node of every bank of pins supporting direct wake-up interrupts (without
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multiplexing) must contain following properties:
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- interrupt-parent: phandle of the interrupt parent to which the external
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wakeup interrupts are forwarded to.
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- interrupts: interrupts of the interrupt parent which are used for external
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wakeup interrupts from pins of the bank, must contain interrupts for all
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pins of the bank.
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Aliases:
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All the pin controller nodes should be represented in the aliases node using
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the following format 'pinctrl{n}' where n is a unique number for the alias.
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Example: A pin-controller node with pin banks:
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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/* ... */
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/* Pin bank without external interrupts */
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gpy0: gpy0 {
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gpio-controller;
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#gpio-cells = <2>;
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};
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/* ... */
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/* Pin bank with external GPIO or muxed wake-up interrupts */
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gpj0: gpj0 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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/* ... */
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/* Pin bank with external direct wake-up interrupts */
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gpx0: gpx0 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
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<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
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#interrupt-cells = <2>;
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};
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/* ... */
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};
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Example 1: A pin-controller node with pin groups.
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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/* ... */
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uart0_data: uart0-data {
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samsung,pins = "gpa0-0", "gpa0-1";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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uart0_fctl: uart0-fctl {
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samsung,pins = "gpa0-2", "gpa0-3";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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uart1_data: uart1-data {
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samsung,pins = "gpa0-4", "gpa0-5";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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uart1_fctl: uart1-fctl {
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samsung,pins = "gpa0-6", "gpa0-7";
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samsung,pin-function = <2>;
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samsung,pin-pud = <0>;
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samsung,pin-drv = <0>;
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};
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i2c2_bus: i2c2-bus {
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samsung,pins = "gpa0-6", "gpa0-7";
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samsung,pin-function = <3>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <0>;
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};
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};
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Example 2: A pin-controller node with external wakeup interrupt controller node.
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4210-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>
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/* ... */
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 32 0>;
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};
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};
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Example 3: A uart client node that supports 'default' and 'flow-control' states.
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uart@13800000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13800000 0x100>;
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interrupts = <0 52 0>;
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pinctrl-names = "default", "flow-control;
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pinctrl-0 = <&uart0_data>;
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pinctrl-1 = <&uart0_data &uart0_fctl>;
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};
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Example 4: Set up the default pin state for uart controller.
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static int s3c24xx_serial_probe(struct platform_device *pdev) {
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struct pinctrl *pinctrl;
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/* ... */
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pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
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}
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Example 5: A display port client node that supports 'default' pinctrl state
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and gpio binding.
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display-port-controller {
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/* ... */
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samsung,hpd-gpio = <&gpx2 6 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&dp_hpd>;
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};
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Example 6: Request the gpio for display port controller
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static int exynos_dp_probe(struct platform_device *pdev)
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{
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int hpd_gpio, ret;
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struct device *dev = &pdev->dev;
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struct device_node *dp_node = dev->of_node;
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/* ... */
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hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
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/* ... */
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ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
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"hpd_gpio");
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/* ... */
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}
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