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Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits" property to configure the number of bits passed through from PCIe address to internal address in Inbound Address Translation register. This only used the NO MATCH BAR. However standard PCI dt-binding already defines "dma-ranges" to describe the address ranges accessible by PCIe controller. Add support in Cadence PCIe host driver to parse dma-ranges and configure the inbound regions for BAR0, BAR1 and NO MATCH BAR. Cadence IP specifies maximum size for BAR0 as 256GB, maximum size for BAR1 as 2 GB. This adds support to take the next biggest region in "dma-ranges" and find the smallest BAR that each of the regions fit in and if there is no BAR big enough to hold the region, split the region to see if it can be fitted using multiple BARs. "dma-ranges" of J721E will be dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; Since there is no BAR which can hold 2^48 size, NO_MATCH_BAR will be used here. Legacy device tree binding compatibility is maintained by retaining support for "cdns,no-bar-match-nbits". Link: https://lore.kernel.org/r/20200722110317.4744-2-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> |
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| .. | ||
| controller | ||
| endpoint | ||
| hotplug | ||
| pcie | ||
| switch | ||
| access.c | ||
| ats.c | ||
| bus.c | ||
| ecam.c | ||
| host-bridge.c | ||
| iov.c | ||
| irq.c | ||
| Kconfig | ||
| Makefile | ||
| mmap.c | ||
| msi.c | ||
| of.c | ||
| p2pdma.c | ||
| pci-acpi.c | ||
| pci-bridge-emul.c | ||
| pci-bridge-emul.h | ||
| pci-driver.c | ||
| pci-label.c | ||
| pci-mid.c | ||
| pci-pf-stub.c | ||
| pci-stub.c | ||
| pci-sysfs.c | ||
| pci.c | ||
| pci.h | ||
| probe.c | ||
| proc.c | ||
| quirks.c | ||
| remove.c | ||
| rom.c | ||
| search.c | ||
| setup-bus.c | ||
| setup-irq.c | ||
| setup-res.c | ||
| slot.c | ||
| syscall.c | ||
| vc.c | ||
| vpd.c | ||
| xen-pcifront.c | ||