Thierry Reding 5d2304c1de dt-bindings: display: tegra: Add source clock for SOR ... The SOR clock can have various sources, with the most commonly used being the sor_safe, pll_d2_out0, pll_dp and sor_brick clocks. These are configured using a three level mux, of which the first 2 levels can be treated as one. The direct parents of the SOR clock are the sor_safe, sor_brick and sor_src clocks, whereas the pll_d2_out0 and pll_dp clocks can be selected as parents of the sor_src clock via a second mux. Previous generations of Tegra have only supported eDP and LVDS with the SOR, where LVDS was never used on publicly available hardware. Clocking for this only ever required the first level mux (to select between sor_safe and sor_brick). Tegra210 has a new revision of the SOR that supports HDMI and hence needs to support the second level mux to allow selecting pll_d2_out0 as the SOR clock's parent. This second mux is knows as sor_src, and operating system software needs a reference to it in order to select the proper parent. Signed-off-by: Thierry Reding <treding@nvidia.com>		2016-07-14 14:57:00 +02:00
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bindings	dt-bindings: display: tegra: Add source clock for SOR	2016-07-14 14:57:00 +02:00
00-INDEX
booting-without-of.txt	sh: add device tree support and generic board using device tree	2016-03-17 19:46:11 +00:00
changesets.txt
dynamic-resolution-notes.txt
of_unittest.txt
overlay-notes.txt
todo.txt
usage-model.txt