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e8cde0939d
Setting up IRQ routes is nothing IOAPIC specific. Extract everything that really is generic code into irqchip.c and only leave the ioapic specific bits to irq_comm.c. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Michael S. Tsirkin <mst@redhat.com>
373 lines
9.9 KiB
C
373 lines
9.9 KiB
C
/*
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* irq_comm.c: Common API for in kernel interrupt controller
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* Copyright (c) 2007, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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* Authors:
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* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
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*
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*/
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#include <linux/kvm_host.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <trace/events/kvm.h>
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#include <asm/msidef.h>
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#ifdef CONFIG_IA64
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#include <asm/iosapic.h>
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#endif
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#include "irq.h"
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#include "ioapic.h"
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static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level,
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bool line_status)
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{
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#ifdef CONFIG_X86
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struct kvm_pic *pic = pic_irqchip(kvm);
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return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
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#else
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return -1;
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#endif
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}
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static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level,
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bool line_status)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
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line_status);
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}
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inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
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{
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#ifdef CONFIG_IA64
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return irq->delivery_mode ==
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(IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
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#else
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return irq->delivery_mode == APIC_DM_LOWEST;
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#endif
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}
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int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
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struct kvm_lapic_irq *irq, unsigned long *dest_map)
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{
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int i, r = -1;
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struct kvm_vcpu *vcpu, *lowest = NULL;
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if (irq->dest_mode == 0 && irq->dest_id == 0xff &&
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kvm_is_dm_lowest_prio(irq)) {
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printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
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irq->delivery_mode = APIC_DM_FIXED;
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}
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if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
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return r;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (!kvm_apic_present(vcpu))
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continue;
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if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
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irq->dest_id, irq->dest_mode))
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continue;
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if (!kvm_is_dm_lowest_prio(irq)) {
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if (r < 0)
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r = 0;
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r += kvm_apic_set_irq(vcpu, irq, dest_map);
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} else if (kvm_lapic_enabled(vcpu)) {
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if (!lowest)
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lowest = vcpu;
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else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
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lowest = vcpu;
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}
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}
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if (lowest)
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r = kvm_apic_set_irq(lowest, irq, dest_map);
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return r;
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}
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static inline void kvm_set_msi_irq(struct kvm_kernel_irq_routing_entry *e,
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struct kvm_lapic_irq *irq)
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{
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trace_kvm_msi_set_irq(e->msi.address_lo, e->msi.data);
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irq->dest_id = (e->msi.address_lo &
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MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
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irq->vector = (e->msi.data &
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MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
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irq->dest_mode = (1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo;
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irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
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irq->delivery_mode = e->msi.data & 0x700;
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irq->level = 1;
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irq->shorthand = 0;
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/* TODO Deal with RH bit of MSI message address */
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}
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int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level, bool line_status)
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{
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struct kvm_lapic_irq irq;
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if (!level)
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return -1;
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kvm_set_msi_irq(e, &irq);
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return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
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}
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static int kvm_set_msi_inatomic(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm)
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{
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struct kvm_lapic_irq irq;
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int r;
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kvm_set_msi_irq(e, &irq);
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if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
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return r;
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else
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return -EWOULDBLOCK;
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}
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/*
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* Deliver an IRQ in an atomic context if we can, or return a failure,
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* user can retry in a process context.
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* Return value:
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* -EWOULDBLOCK - Can't deliver in atomic context: retry in a process context.
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* Other values - No need to retry.
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*/
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int kvm_set_irq_inatomic(struct kvm *kvm, int irq_source_id, u32 irq, int level)
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{
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struct kvm_kernel_irq_routing_entry *e;
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int ret = -EINVAL;
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struct kvm_irq_routing_table *irq_rt;
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trace_kvm_set_irq(irq, level, irq_source_id);
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/*
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* Injection into either PIC or IOAPIC might need to scan all CPUs,
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* which would need to be retried from thread context; when same GSI
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* is connected to both PIC and IOAPIC, we'd have to report a
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* partial failure here.
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* Since there's no easy way to do this, we only support injecting MSI
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* which is limited to 1:1 GSI mapping.
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*/
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rcu_read_lock();
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irq_rt = rcu_dereference(kvm->irq_routing);
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if (irq < irq_rt->nr_rt_entries)
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hlist_for_each_entry(e, &irq_rt->map[irq], link) {
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if (likely(e->type == KVM_IRQ_ROUTING_MSI))
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ret = kvm_set_msi_inatomic(e, kvm);
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else
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ret = -EWOULDBLOCK;
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break;
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}
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rcu_read_unlock();
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return ret;
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}
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int kvm_request_irq_source_id(struct kvm *kvm)
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{
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unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
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int irq_source_id;
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mutex_lock(&kvm->irq_lock);
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irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);
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if (irq_source_id >= BITS_PER_LONG) {
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printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
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irq_source_id = -EFAULT;
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goto unlock;
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}
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ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
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#ifdef CONFIG_X86
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ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
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#endif
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set_bit(irq_source_id, bitmap);
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unlock:
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mutex_unlock(&kvm->irq_lock);
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return irq_source_id;
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}
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void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
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{
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ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
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#ifdef CONFIG_X86
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ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
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#endif
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mutex_lock(&kvm->irq_lock);
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if (irq_source_id < 0 ||
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irq_source_id >= BITS_PER_LONG) {
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printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
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goto unlock;
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}
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clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
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if (!irqchip_in_kernel(kvm))
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goto unlock;
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kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
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#ifdef CONFIG_X86
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kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
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#endif
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unlock:
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mutex_unlock(&kvm->irq_lock);
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}
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void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
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struct kvm_irq_mask_notifier *kimn)
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{
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mutex_lock(&kvm->irq_lock);
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kimn->irq = irq;
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hlist_add_head_rcu(&kimn->link, &kvm->mask_notifier_list);
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mutex_unlock(&kvm->irq_lock);
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}
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void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
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struct kvm_irq_mask_notifier *kimn)
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{
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mutex_lock(&kvm->irq_lock);
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hlist_del_rcu(&kimn->link);
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mutex_unlock(&kvm->irq_lock);
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synchronize_rcu();
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}
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void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
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bool mask)
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{
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struct kvm_irq_mask_notifier *kimn;
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int gsi;
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rcu_read_lock();
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gsi = rcu_dereference(kvm->irq_routing)->chip[irqchip][pin];
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if (gsi != -1)
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hlist_for_each_entry_rcu(kimn, &kvm->mask_notifier_list, link)
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if (kimn->irq == gsi)
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kimn->func(kimn, mask);
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rcu_read_unlock();
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}
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int kvm_set_routing_entry(struct kvm_irq_routing_table *rt,
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struct kvm_kernel_irq_routing_entry *e,
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const struct kvm_irq_routing_entry *ue)
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{
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int r = -EINVAL;
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int delta;
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unsigned max_pin;
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switch (ue->type) {
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case KVM_IRQ_ROUTING_IRQCHIP:
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delta = 0;
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switch (ue->u.irqchip.irqchip) {
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case KVM_IRQCHIP_PIC_MASTER:
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e->set = kvm_set_pic_irq;
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max_pin = PIC_NUM_PINS;
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break;
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case KVM_IRQCHIP_PIC_SLAVE:
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e->set = kvm_set_pic_irq;
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max_pin = PIC_NUM_PINS;
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delta = 8;
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break;
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case KVM_IRQCHIP_IOAPIC:
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max_pin = KVM_IOAPIC_NUM_PINS;
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e->set = kvm_set_ioapic_irq;
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break;
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default:
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goto out;
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}
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e->irqchip.irqchip = ue->u.irqchip.irqchip;
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e->irqchip.pin = ue->u.irqchip.pin + delta;
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if (e->irqchip.pin >= max_pin)
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goto out;
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rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi;
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break;
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case KVM_IRQ_ROUTING_MSI:
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e->set = kvm_set_msi;
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e->msi.address_lo = ue->u.msi.address_lo;
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e->msi.address_hi = ue->u.msi.address_hi;
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e->msi.data = ue->u.msi.data;
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break;
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default:
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goto out;
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}
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r = 0;
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out:
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return r;
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}
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#define IOAPIC_ROUTING_ENTRY(irq) \
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{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
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.u.irqchip.irqchip = KVM_IRQCHIP_IOAPIC, .u.irqchip.pin = (irq) }
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#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
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#ifdef CONFIG_X86
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# define PIC_ROUTING_ENTRY(irq) \
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{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
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.u.irqchip.irqchip = SELECT_PIC(irq), .u.irqchip.pin = (irq) % 8 }
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# define ROUTING_ENTRY2(irq) \
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IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
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#else
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# define ROUTING_ENTRY2(irq) \
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IOAPIC_ROUTING_ENTRY(irq)
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#endif
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static const struct kvm_irq_routing_entry default_routing[] = {
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ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
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ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
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ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
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ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
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ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
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ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
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ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
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ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
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ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
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ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
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ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
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ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
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#ifdef CONFIG_IA64
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ROUTING_ENTRY1(24), ROUTING_ENTRY1(25),
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ROUTING_ENTRY1(26), ROUTING_ENTRY1(27),
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ROUTING_ENTRY1(28), ROUTING_ENTRY1(29),
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ROUTING_ENTRY1(30), ROUTING_ENTRY1(31),
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ROUTING_ENTRY1(32), ROUTING_ENTRY1(33),
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ROUTING_ENTRY1(34), ROUTING_ENTRY1(35),
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ROUTING_ENTRY1(36), ROUTING_ENTRY1(37),
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ROUTING_ENTRY1(38), ROUTING_ENTRY1(39),
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ROUTING_ENTRY1(40), ROUTING_ENTRY1(41),
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ROUTING_ENTRY1(42), ROUTING_ENTRY1(43),
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ROUTING_ENTRY1(44), ROUTING_ENTRY1(45),
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ROUTING_ENTRY1(46), ROUTING_ENTRY1(47),
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#endif
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};
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int kvm_setup_default_irq_routing(struct kvm *kvm)
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{
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return kvm_set_irq_routing(kvm, default_routing,
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ARRAY_SIZE(default_routing), 0);
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}
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