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5f2f5eaa3e
It makes no sense to leave crc32_be using the generic code while we
only accelerate the little-endian ops.
Even though the big-endian form doesn't fit as smoothly into the arm64,
we can speed it up and avoid hitting the D cache.
Tested on Cortex-A53. Without acceleration:
crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64
crc32: self tests passed, processed 225944 bytes in 192240 nsec
crc32c: CRC_LE_BITS = 64
crc32c: self tests passed, processed 112972 bytes in 21360 nsec
With acceleration:
crc32: CRC_LE_BITS = 64, CRC_BE BITS = 64
crc32: self tests passed, processed 225944 bytes in 53480 nsec
crc32c: CRC_LE_BITS = 64
crc32c: self tests passed, processed 112972 bytes in 21480 nsec
Signed-off-by: Kevin Bracey <kevin@bracey.fi>
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
161 lines
2.8 KiB
ArmAsm
161 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Accelerated CRC32(C) using AArch64 CRC instructions
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*
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* Copyright (C) 2016 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
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*/
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/assembler.h>
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.arch armv8-a+crc
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.macro byteorder, reg, be
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.if \be
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CPU_LE( rev \reg, \reg )
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.else
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CPU_BE( rev \reg, \reg )
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.endif
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.endm
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.macro byteorder16, reg, be
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.if \be
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CPU_LE( rev16 \reg, \reg )
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.else
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CPU_BE( rev16 \reg, \reg )
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.endif
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.endm
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.macro bitorder, reg, be
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.if \be
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rbit \reg, \reg
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.endif
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.endm
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.macro bitorder16, reg, be
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.if \be
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rbit \reg, \reg
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lsr \reg, \reg, #16
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.endif
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.endm
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.macro bitorder8, reg, be
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.if \be
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rbit \reg, \reg
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lsr \reg, \reg, #24
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.endif
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.endm
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.macro __crc32, c, be=0
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bitorder w0, \be
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cmp x2, #16
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b.lt 8f // less than 16 bytes
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and x7, x2, #0x1f
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and x2, x2, #~0x1f
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cbz x7, 32f // multiple of 32 bytes
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and x8, x7, #0xf
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ldp x3, x4, [x1]
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add x8, x8, x1
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add x1, x1, x7
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ldp x5, x6, [x8]
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byteorder x3, \be
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byteorder x4, \be
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byteorder x5, \be
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byteorder x6, \be
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bitorder x3, \be
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bitorder x4, \be
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bitorder x5, \be
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bitorder x6, \be
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tst x7, #8
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crc32\c\()x w8, w0, x3
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csel x3, x3, x4, eq
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csel w0, w0, w8, eq
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tst x7, #4
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lsr x4, x3, #32
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crc32\c\()w w8, w0, w3
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csel x3, x3, x4, eq
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csel w0, w0, w8, eq
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tst x7, #2
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lsr w4, w3, #16
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crc32\c\()h w8, w0, w3
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csel w3, w3, w4, eq
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csel w0, w0, w8, eq
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tst x7, #1
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crc32\c\()b w8, w0, w3
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csel w0, w0, w8, eq
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tst x7, #16
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crc32\c\()x w8, w0, x5
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crc32\c\()x w8, w8, x6
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csel w0, w0, w8, eq
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cbz x2, 0f
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32: ldp x3, x4, [x1], #32
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sub x2, x2, #32
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ldp x5, x6, [x1, #-16]
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byteorder x3, \be
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byteorder x4, \be
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byteorder x5, \be
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byteorder x6, \be
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bitorder x3, \be
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bitorder x4, \be
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bitorder x5, \be
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bitorder x6, \be
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crc32\c\()x w0, w0, x3
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crc32\c\()x w0, w0, x4
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crc32\c\()x w0, w0, x5
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crc32\c\()x w0, w0, x6
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cbnz x2, 32b
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0: bitorder w0, \be
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ret
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8: tbz x2, #3, 4f
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ldr x3, [x1], #8
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byteorder x3, \be
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bitorder x3, \be
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crc32\c\()x w0, w0, x3
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4: tbz x2, #2, 2f
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ldr w3, [x1], #4
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byteorder w3, \be
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bitorder w3, \be
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crc32\c\()w w0, w0, w3
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2: tbz x2, #1, 1f
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ldrh w3, [x1], #2
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byteorder16 w3, \be
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bitorder16 w3, \be
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crc32\c\()h w0, w0, w3
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1: tbz x2, #0, 0f
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ldrb w3, [x1]
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bitorder8 w3, \be
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crc32\c\()b w0, w0, w3
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0: bitorder w0, \be
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ret
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.endm
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.align 5
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SYM_FUNC_START(crc32_le)
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alternative_if_not ARM64_HAS_CRC32
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b crc32_le_base
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alternative_else_nop_endif
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__crc32
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SYM_FUNC_END(crc32_le)
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.align 5
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SYM_FUNC_START(__crc32c_le)
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alternative_if_not ARM64_HAS_CRC32
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b __crc32c_le_base
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alternative_else_nop_endif
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__crc32 c
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SYM_FUNC_END(__crc32c_le)
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.align 5
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SYM_FUNC_START(crc32_be)
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alternative_if_not ARM64_HAS_CRC32
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b crc32_be_base
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alternative_else_nop_endif
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__crc32 be=1
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SYM_FUNC_END(crc32_be)
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