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The current cache options don't really represent the hardware features. They end up setting different aspects of the hardware so that the end result is to turn on/off the cache. Unfortunately, when we hit cache problems with the hardware, it's difficult to test different settings to root cause the problem. The current settings also don't cleanly allow for different caching behaviors with different regions of memory. So split the configure options such that they properly reflect the settings that are applied to the hardware. Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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* Blackfin CPLB initialization
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*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#include <asm/mem_map.h>
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#if ANOMALY_05000263
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# error the MPU will not function safely while Anomaly 05000263 applies
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#endif
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struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
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struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
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int first_switched_icplb, first_switched_dcplb;
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int first_mask_dcplb;
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void __init generate_cplb_tables_cpu(unsigned int cpu)
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{
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int i_d, i_i;
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unsigned long addr;
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unsigned long d_data, i_data;
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unsigned long d_cache = 0, i_cache = 0;
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printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
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#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
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i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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#endif
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#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
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d_cache = CPLB_L1_CHBL;
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#ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH
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d_cache |= CPLB_L1_AOW | CPLB_WT;
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#endif
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#endif
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i_d = i_i = 0;
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/* Set up the zero page. */
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dcplb_tbl[cpu][i_d].addr = 0;
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dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
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icplb_tbl[cpu][i_i].addr = 0;
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icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
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/* Cover kernel memory with 4M pages. */
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addr = 0;
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d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
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i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
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for (; addr < memory_start; addr += 4 * 1024 * 1024) {
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dcplb_tbl[cpu][i_d].addr = addr;
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dcplb_tbl[cpu][i_d++].data = d_data;
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icplb_tbl[cpu][i_i].addr = addr;
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icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
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}
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/* Cover L1 memory. One 4M area for code and data each is enough. */
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#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
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dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
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dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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#endif
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#if L1_CODE_LENGTH > 0
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icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
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icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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#endif
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/* Cover L2 memory */
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#if L2_LENGTH > 0
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dcplb_tbl[cpu][i_d].addr = L2_START;
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dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
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icplb_tbl[cpu][i_i].addr = L2_START;
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icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
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#endif
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first_mask_dcplb = i_d;
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first_switched_dcplb = i_d + (1 << page_mask_order);
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first_switched_icplb = i_i;
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while (i_d < MAX_CPLBS)
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dcplb_tbl[cpu][i_d++].data = 0;
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while (i_i < MAX_CPLBS)
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icplb_tbl[cpu][i_i++].data = 0;
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}
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void generate_cplb_tables_all(void)
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{
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}
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