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84ec985944
When CXL subsystem is auto-assembling a pmem region during cxl
endpoint port probing, always hit below calltrace.
BUG: kernel NULL pointer dereference, address: 0000000000000078
#PF: supervisor read access in kernel mode
#PF: error_code(0x0000) - not-present page
RIP: 0010:cxl_pmem_region_probe+0x22e/0x360 [cxl_pmem]
Call Trace:
<TASK>
? __die+0x24/0x70
? page_fault_oops+0x82/0x160
? do_user_addr_fault+0x65/0x6b0
? exc_page_fault+0x7d/0x170
? asm_exc_page_fault+0x26/0x30
? cxl_pmem_region_probe+0x22e/0x360 [cxl_pmem]
? cxl_pmem_region_probe+0x1ac/0x360 [cxl_pmem]
cxl_bus_probe+0x1b/0x60 [cxl_core]
really_probe+0x173/0x410
? __pfx___device_attach_driver+0x10/0x10
__driver_probe_device+0x80/0x170
driver_probe_device+0x1e/0x90
__device_attach_driver+0x90/0x120
bus_for_each_drv+0x84/0xe0
__device_attach+0xbc/0x1f0
bus_probe_device+0x90/0xa0
device_add+0x51c/0x710
devm_cxl_add_pmem_region+0x1b5/0x380 [cxl_core]
cxl_bus_probe+0x1b/0x60 [cxl_core]
The cxl_nvd of the memdev needs to be available during the pmem region
probe. Currently the cxl_nvd is registered after the endpoint port probe.
The endpoint probe, in the case of autoassembly of regions, can cause a
pmem region probe requiring the not yet available cxl_nvd. Adjust the
sequence so this dependency is met.
This requires adding a port parameter to cxl_find_nvdimm_bridge() that
can be used to query the ancestor root port. The endpoint port is not
yet available, but will share a common ancestor with its parent, so
start the query from there instead.
Fixes: f17b558d66
("cxl/pmem: Refactor nvdimm device registration, delete the workqueue")
Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Li Ming <ming4.li@intel.com>
Tested-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240612064423.2567625-1-ming4.li@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
297 lines
7.2 KiB
C
297 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2020 Intel Corporation. */
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/idr.h>
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#include <cxlmem.h>
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#include <cxl.h>
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#include "core.h"
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/**
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* DOC: cxl pmem
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*
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* The core CXL PMEM infrastructure supports persistent memory
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* provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL
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* 'bridge' device is added at the root of a CXL device topology if
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* platform firmware advertises at least one persistent memory capable
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* CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus'
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* device. Then for each cxl_memdev in the CXL device topology a bridge
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* device is added to host a LIBNVDIMM dimm object. When these bridges
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* are registered native LIBNVDIMM uapis are translated to CXL
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* operations, for example, namespace label access commands.
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*/
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static DEFINE_IDA(cxl_nvdimm_bridge_ida);
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static void cxl_nvdimm_bridge_release(struct device *dev)
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{
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struct cxl_nvdimm_bridge *cxl_nvb = to_cxl_nvdimm_bridge(dev);
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ida_free(&cxl_nvdimm_bridge_ida, cxl_nvb->id);
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kfree(cxl_nvb);
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}
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static const struct attribute_group *cxl_nvdimm_bridge_attribute_groups[] = {
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&cxl_base_attribute_group,
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NULL,
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};
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const struct device_type cxl_nvdimm_bridge_type = {
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.name = "cxl_nvdimm_bridge",
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.release = cxl_nvdimm_bridge_release,
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.groups = cxl_nvdimm_bridge_attribute_groups,
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};
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struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev)
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{
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if (dev_WARN_ONCE(dev, dev->type != &cxl_nvdimm_bridge_type,
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"not a cxl_nvdimm_bridge device\n"))
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return NULL;
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return container_of(dev, struct cxl_nvdimm_bridge, dev);
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}
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EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm_bridge, CXL);
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bool is_cxl_nvdimm_bridge(struct device *dev)
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{
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return dev->type == &cxl_nvdimm_bridge_type;
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}
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EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm_bridge, CXL);
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static int match_nvdimm_bridge(struct device *dev, void *data)
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{
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return is_cxl_nvdimm_bridge(dev);
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}
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/**
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* cxl_find_nvdimm_bridge() - find a bridge device relative to a port
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* @port: any descendant port of an nvdimm-bridge associated
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* root-cxl-port
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*/
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port)
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{
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struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);
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struct device *dev;
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if (!cxl_root)
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return NULL;
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dev = device_find_child(&cxl_root->port.dev, NULL, match_nvdimm_bridge);
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if (!dev)
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return NULL;
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return to_cxl_nvdimm_bridge(dev);
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}
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EXPORT_SYMBOL_NS_GPL(cxl_find_nvdimm_bridge, CXL);
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static struct lock_class_key cxl_nvdimm_bridge_key;
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static struct cxl_nvdimm_bridge *cxl_nvdimm_bridge_alloc(struct cxl_port *port)
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{
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct device *dev;
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int rc;
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cxl_nvb = kzalloc(sizeof(*cxl_nvb), GFP_KERNEL);
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if (!cxl_nvb)
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return ERR_PTR(-ENOMEM);
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rc = ida_alloc(&cxl_nvdimm_bridge_ida, GFP_KERNEL);
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if (rc < 0)
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goto err;
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cxl_nvb->id = rc;
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dev = &cxl_nvb->dev;
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cxl_nvb->port = port;
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device_initialize(dev);
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lockdep_set_class(&dev->mutex, &cxl_nvdimm_bridge_key);
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device_set_pm_not_required(dev);
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dev->parent = &port->dev;
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dev->bus = &cxl_bus_type;
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dev->type = &cxl_nvdimm_bridge_type;
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return cxl_nvb;
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err:
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kfree(cxl_nvb);
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return ERR_PTR(rc);
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}
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static void unregister_nvb(void *_cxl_nvb)
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{
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struct cxl_nvdimm_bridge *cxl_nvb = _cxl_nvb;
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device_unregister(&cxl_nvb->dev);
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}
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/**
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* devm_cxl_add_nvdimm_bridge() - add the root of a LIBNVDIMM topology
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* @host: platform firmware root device
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* @port: CXL port at the root of a CXL topology
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*
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* Return: bridge device that can host cxl_nvdimm objects
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*/
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struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
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struct cxl_port *port)
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{
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct device *dev;
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int rc;
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if (!IS_ENABLED(CONFIG_CXL_PMEM))
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return ERR_PTR(-ENXIO);
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cxl_nvb = cxl_nvdimm_bridge_alloc(port);
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if (IS_ERR(cxl_nvb))
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return cxl_nvb;
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dev = &cxl_nvb->dev;
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rc = dev_set_name(dev, "nvdimm-bridge%d", cxl_nvb->id);
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if (rc)
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goto err;
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rc = device_add(dev);
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if (rc)
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goto err;
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rc = devm_add_action_or_reset(host, unregister_nvb, cxl_nvb);
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if (rc)
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return ERR_PTR(rc);
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return cxl_nvb;
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err:
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put_device(dev);
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return ERR_PTR(rc);
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_nvdimm_bridge, CXL);
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static void cxl_nvdimm_release(struct device *dev)
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{
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struct cxl_nvdimm *cxl_nvd = to_cxl_nvdimm(dev);
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kfree(cxl_nvd);
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}
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static const struct attribute_group *cxl_nvdimm_attribute_groups[] = {
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&cxl_base_attribute_group,
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NULL,
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};
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const struct device_type cxl_nvdimm_type = {
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.name = "cxl_nvdimm",
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.release = cxl_nvdimm_release,
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.groups = cxl_nvdimm_attribute_groups,
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};
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bool is_cxl_nvdimm(struct device *dev)
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{
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return dev->type == &cxl_nvdimm_type;
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}
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EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm, CXL);
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struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev)
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{
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if (dev_WARN_ONCE(dev, !is_cxl_nvdimm(dev),
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"not a cxl_nvdimm device\n"))
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return NULL;
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return container_of(dev, struct cxl_nvdimm, dev);
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}
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EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm, CXL);
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static struct lock_class_key cxl_nvdimm_key;
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static struct cxl_nvdimm *cxl_nvdimm_alloc(struct cxl_nvdimm_bridge *cxl_nvb,
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struct cxl_memdev *cxlmd)
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{
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struct cxl_nvdimm *cxl_nvd;
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struct device *dev;
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cxl_nvd = kzalloc(sizeof(*cxl_nvd), GFP_KERNEL);
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if (!cxl_nvd)
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return ERR_PTR(-ENOMEM);
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dev = &cxl_nvd->dev;
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cxl_nvd->cxlmd = cxlmd;
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cxlmd->cxl_nvd = cxl_nvd;
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device_initialize(dev);
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lockdep_set_class(&dev->mutex, &cxl_nvdimm_key);
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device_set_pm_not_required(dev);
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dev->parent = &cxlmd->dev;
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dev->bus = &cxl_bus_type;
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dev->type = &cxl_nvdimm_type;
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/*
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* A "%llx" string is 17-bytes vs dimm_id that is max
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* NVDIMM_KEY_DESC_LEN
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*/
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BUILD_BUG_ON(sizeof(cxl_nvd->dev_id) < 17 ||
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sizeof(cxl_nvd->dev_id) > NVDIMM_KEY_DESC_LEN);
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sprintf(cxl_nvd->dev_id, "%llx", cxlmd->cxlds->serial);
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return cxl_nvd;
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}
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static void cxlmd_release_nvdimm(void *_cxlmd)
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{
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struct cxl_memdev *cxlmd = _cxlmd;
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struct cxl_nvdimm *cxl_nvd = cxlmd->cxl_nvd;
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struct cxl_nvdimm_bridge *cxl_nvb = cxlmd->cxl_nvb;
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cxl_nvd->cxlmd = NULL;
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cxlmd->cxl_nvd = NULL;
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cxlmd->cxl_nvb = NULL;
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device_unregister(&cxl_nvd->dev);
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put_device(&cxl_nvb->dev);
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}
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/**
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* devm_cxl_add_nvdimm() - add a bridge between a cxl_memdev and an nvdimm
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* @parent_port: parent port for the (to be added) @cxlmd endpoint port
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* @cxlmd: cxl_memdev instance that will perform LIBNVDIMM operations
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*
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* Return: 0 on success negative error code on failure.
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*/
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int devm_cxl_add_nvdimm(struct cxl_port *parent_port,
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struct cxl_memdev *cxlmd)
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{
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct cxl_nvdimm *cxl_nvd;
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struct device *dev;
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int rc;
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cxl_nvb = cxl_find_nvdimm_bridge(parent_port);
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if (!cxl_nvb)
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return -ENODEV;
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cxl_nvd = cxl_nvdimm_alloc(cxl_nvb, cxlmd);
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if (IS_ERR(cxl_nvd)) {
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rc = PTR_ERR(cxl_nvd);
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goto err_alloc;
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}
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cxlmd->cxl_nvb = cxl_nvb;
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dev = &cxl_nvd->dev;
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rc = dev_set_name(dev, "pmem%d", cxlmd->id);
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if (rc)
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goto err;
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rc = device_add(dev);
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if (rc)
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goto err;
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dev_dbg(&cxlmd->dev, "register %s\n", dev_name(dev));
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/* @cxlmd carries a reference on @cxl_nvb until cxlmd_release_nvdimm */
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return devm_add_action_or_reset(&cxlmd->dev, cxlmd_release_nvdimm, cxlmd);
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err:
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put_device(dev);
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err_alloc:
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cxlmd->cxl_nvb = NULL;
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cxlmd->cxl_nvd = NULL;
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put_device(&cxl_nvb->dev);
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return rc;
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}
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EXPORT_SYMBOL_NS_GPL(devm_cxl_add_nvdimm, CXL);
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