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add a DT binding documentation of usb3.0 phy for MT65xx SoCs from Mediatek. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
69 lines
1.8 KiB
Plaintext
69 lines
1.8 KiB
Plaintext
mt65xx USB3.0 PHY binding
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--------------------------
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This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
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Required properties (controller (parent) node):
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- compatible : should be "mediatek,mt8173-u3phy"
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- reg : offset and length of register for phy, exclude port's
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register.
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- clocks : a list of phandle + clock-specifier pairs, one for each
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entry in clock-names
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- clock-names : must contain
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"u3phya_ref": for reference clock of usb3.0 analog phy.
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Required nodes : a sub-node is required for each port the controller
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provides. Address range information including the usual
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'reg' property is used inside these nodes to describe
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the controller's topology.
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Required properties (port (child) node):
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- reg : address and length of the register set for the port.
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- #phy-cells : should be 1 (See second example)
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cell after port phandle is phy type from:
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- PHY_TYPE_USB2
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- PHY_TYPE_USB3
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Example:
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u3phy: usb-phy@11290000 {
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compatible = "mediatek,mt8173-u3phy";
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reg = <0 0x11290000 0 0x800>;
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clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
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clock-names = "u3phya_ref";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "okay";
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phy_port0: port@11290800 {
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reg = <0 0x11290800 0 0x800>;
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#phy-cells = <1>;
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status = "okay";
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};
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phy_port1: port@11291000 {
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reg = <0 0x11291000 0 0x800>;
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#phy-cells = <1>;
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status = "okay";
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};
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};
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Specifying phy control of devices
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---------------------------------
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Device nodes should specify the configuration required in their "phys"
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property, containing a phandle to the phy port node and a device type;
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phy-names for each port are optional.
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Example:
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#include <dt-bindings/phy/phy.h>
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usb30: usb@11270000 {
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...
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phys = <&phy_port0 PHY_TYPE_USB3>;
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phy-names = "usb3-0";
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...
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};
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