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5a8d5441f4
DA850/OMAP-L138 has 144 pins configurable as GPIO, but currently this has been configured as 128. This patch corrects it. Also, this patch adds the base address for GPIO pins greater than 128. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
636 lines
16 KiB
C
636 lines
16 KiB
C
/*
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* TI DA850/OMAP-L138 chip specific setup
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*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Derived from: arch/arm/mach-davinci/da830.c
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* Original Copyrights follow:
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*
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* 2009 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <asm/mach/map.h>
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#include <mach/clock.h>
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#include <mach/psc.h>
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#include <mach/mux.h>
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#include <mach/irqs.h>
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#include <mach/cputype.h>
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#include <mach/common.h>
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#include <mach/time.h>
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#include <mach/da8xx.h>
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#include "clock.h"
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#include "mux.h"
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#define DA850_PLL1_BASE 0x01e1a000
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#define DA850_TIMER64P2_BASE 0x01f0c000
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#define DA850_TIMER64P3_BASE 0x01f0d000
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#define DA850_REF_FREQ 24000000
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static struct pll_data pll0_data = {
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.num = 1,
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.phys_base = DA8XX_PLL0_BASE,
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.flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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.rate = DA850_REF_FREQ,
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};
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static struct clk pll0_clk = {
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.name = "pll0",
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.parent = &ref_clk,
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.pll_data = &pll0_data,
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.flags = CLK_PLL,
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};
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static struct clk pll0_aux_clk = {
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.name = "pll0_aux_clk",
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.parent = &pll0_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll0_sysclk2 = {
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.name = "pll0_sysclk2",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll0_sysclk3 = {
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.name = "pll0_sysclk3",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll0_sysclk4 = {
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.name = "pll0_sysclk4",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV4,
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};
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static struct clk pll0_sysclk5 = {
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.name = "pll0_sysclk5",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV5,
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};
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static struct clk pll0_sysclk6 = {
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.name = "pll0_sysclk6",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV6,
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};
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static struct clk pll0_sysclk7 = {
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.name = "pll0_sysclk7",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV7,
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};
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static struct pll_data pll1_data = {
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.num = 2,
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.phys_base = DA850_PLL1_BASE,
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.flags = PLL_HAS_POSTDIV,
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};
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static struct clk pll1_clk = {
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.name = "pll1",
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.parent = &ref_clk,
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.pll_data = &pll1_data,
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.flags = CLK_PLL,
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};
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static struct clk pll1_aux_clk = {
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.name = "pll1_aux_clk",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclk2 = {
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.name = "pll1_sysclk2",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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.name = "pll1_sysclk3",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll1_sysclk4 = {
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.name = "pll1_sysclk4",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV4,
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};
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static struct clk pll1_sysclk5 = {
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.name = "pll1_sysclk5",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV5,
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};
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static struct clk pll1_sysclk6 = {
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.name = "pll0_sysclk6",
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV6,
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};
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static struct clk pll1_sysclk7 = {
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.name = "pll1_sysclk7",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV7,
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};
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static struct clk i2c0_clk = {
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.name = "i2c0",
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.parent = &pll0_aux_clk,
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};
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static struct clk timerp64_0_clk = {
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.name = "timer0",
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.parent = &pll0_aux_clk,
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};
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static struct clk timerp64_1_clk = {
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.name = "timer1",
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.parent = &pll0_aux_clk,
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};
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static struct clk arm_rom_clk = {
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.name = "arm_rom",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk tpcc0_clk = {
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.name = "tpcc0",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC0_TPCC,
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.flags = ALWAYS_ENABLED | CLK_PSC,
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};
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static struct clk tptc0_clk = {
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.name = "tptc0",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC0_TPTC0,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk tptc1_clk = {
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.name = "tptc1",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC0_TPTC1,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk tpcc1_clk = {
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.name = "tpcc1",
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.parent = &pll0_sysclk2,
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.lpsc = DA850_LPSC1_TPCC1,
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.flags = CLK_PSC | ALWAYS_ENABLED,
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.psc_ctlr = 1,
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};
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static struct clk tptc2_clk = {
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.name = "tptc2",
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.parent = &pll0_sysclk2,
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.lpsc = DA850_LPSC1_TPTC2,
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.flags = ALWAYS_ENABLED,
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.psc_ctlr = 1,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC0_UART0,
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};
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static struct clk uart1_clk = {
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.name = "uart1",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC1_UART1,
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.psc_ctlr = 1,
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};
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static struct clk uart2_clk = {
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.name = "uart2",
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.parent = &pll0_sysclk2,
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.lpsc = DA8XX_LPSC1_UART2,
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.psc_ctlr = 1,
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};
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static struct clk aintc_clk = {
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.name = "aintc",
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.parent = &pll0_sysclk4,
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.lpsc = DA8XX_LPSC0_AINTC,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk gpio_clk = {
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.name = "gpio",
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.parent = &pll0_sysclk4,
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.lpsc = DA8XX_LPSC1_GPIO,
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.psc_ctlr = 1,
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};
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static struct clk i2c1_clk = {
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.name = "i2c1",
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.parent = &pll0_sysclk4,
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.lpsc = DA8XX_LPSC1_I2C,
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.psc_ctlr = 1,
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};
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static struct clk emif3_clk = {
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.name = "emif3",
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.parent = &pll0_sysclk5,
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.lpsc = DA8XX_LPSC1_EMIF3C,
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.flags = ALWAYS_ENABLED,
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.psc_ctlr = 1,
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};
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static struct clk arm_clk = {
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.name = "arm",
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.parent = &pll0_sysclk6,
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.lpsc = DA8XX_LPSC0_ARM,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk rmii_clk = {
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.name = "rmii",
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.parent = &pll0_sysclk7,
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};
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static struct clk emac_clk = {
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.name = "emac",
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.parent = &pll0_sysclk4,
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.lpsc = DA8XX_LPSC1_CPGMAC,
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.psc_ctlr = 1,
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};
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static struct davinci_clk da850_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll0", &pll0_clk),
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CLK(NULL, "pll0_aux", &pll0_aux_clk),
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CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
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CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
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CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
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CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
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CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
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CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
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CLK(NULL, "pll1", &pll1_clk),
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CLK(NULL, "pll1_aux", &pll1_aux_clk),
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CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
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CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
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CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
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CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
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CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
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CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
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CLK("i2c_davinci.1", NULL, &i2c0_clk),
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CLK(NULL, "timer0", &timerp64_0_clk),
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CLK("watchdog", NULL, &timerp64_1_clk),
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CLK(NULL, "arm_rom", &arm_rom_clk),
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CLK(NULL, "tpcc0", &tpcc0_clk),
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CLK(NULL, "tptc0", &tptc0_clk),
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CLK(NULL, "tptc1", &tptc1_clk),
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CLK(NULL, "tpcc1", &tpcc1_clk),
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CLK(NULL, "tptc2", &tptc2_clk),
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CLK(NULL, "uart0", &uart0_clk),
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CLK(NULL, "uart1", &uart1_clk),
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CLK(NULL, "uart2", &uart2_clk),
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CLK(NULL, "aintc", &aintc_clk),
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CLK(NULL, "gpio", &gpio_clk),
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CLK("i2c_davinci.2", NULL, &i2c1_clk),
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CLK(NULL, "emif3", &emif3_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK(NULL, "rmii", &rmii_clk),
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CLK("davinci_emac.1", NULL, &emac_clk),
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CLK(NULL, NULL, NULL),
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};
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/*
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* Device specific mux setup
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*
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* soc description mux mode mode mux dbg
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* reg offset mask mode
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*/
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static const struct mux_config da850_pins[] = {
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#ifdef CONFIG_DAVINCI_MUX
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/* UART0 function */
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MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
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MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
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MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
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MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
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/* UART1 function */
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MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
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MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
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/* UART2 function */
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MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
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MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
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/* I2C1 function */
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MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
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MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
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/* I2C0 function */
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MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
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MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
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/* EMAC function */
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MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
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MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
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MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
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MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
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MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
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MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
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MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
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MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
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MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
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MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
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MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
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MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
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MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
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MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
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MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
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MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
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MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
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#endif
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};
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const short da850_uart0_pins[] __initdata = {
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DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
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-1
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};
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const short da850_uart1_pins[] __initdata = {
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DA850_UART1_RXD, DA850_UART1_TXD,
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-1
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};
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const short da850_uart2_pins[] __initdata = {
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DA850_UART2_RXD, DA850_UART2_TXD,
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-1
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};
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const short da850_i2c0_pins[] __initdata = {
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DA850_I2C0_SDA, DA850_I2C0_SCL,
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-1
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};
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const short da850_i2c1_pins[] __initdata = {
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DA850_I2C1_SCL, DA850_I2C1_SDA,
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-1
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};
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const short da850_cpgmac_pins[] __initdata = {
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DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
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DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
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DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
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DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
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DA850_MDIO_D,
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-1
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};
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/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
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static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
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[IRQ_DA8XX_COMMTX] = 7,
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[IRQ_DA8XX_COMMRX] = 7,
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[IRQ_DA8XX_NINT] = 7,
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[IRQ_DA8XX_EVTOUT0] = 7,
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[IRQ_DA8XX_EVTOUT1] = 7,
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[IRQ_DA8XX_EVTOUT2] = 7,
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[IRQ_DA8XX_EVTOUT3] = 7,
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[IRQ_DA8XX_EVTOUT4] = 7,
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[IRQ_DA8XX_EVTOUT5] = 7,
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[IRQ_DA8XX_EVTOUT6] = 7,
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[IRQ_DA8XX_EVTOUT6] = 7,
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[IRQ_DA8XX_EVTOUT7] = 7,
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[IRQ_DA8XX_CCINT0] = 7,
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[IRQ_DA8XX_CCERRINT] = 7,
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[IRQ_DA8XX_TCERRINT0] = 7,
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[IRQ_DA8XX_AEMIFINT] = 7,
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[IRQ_DA8XX_I2CINT0] = 7,
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[IRQ_DA8XX_MMCSDINT0] = 7,
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[IRQ_DA8XX_MMCSDINT1] = 7,
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[IRQ_DA8XX_ALLINT0] = 7,
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[IRQ_DA8XX_RTC] = 7,
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[IRQ_DA8XX_SPINT0] = 7,
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[IRQ_DA8XX_TINT12_0] = 7,
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[IRQ_DA8XX_TINT34_0] = 7,
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[IRQ_DA8XX_TINT12_1] = 7,
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[IRQ_DA8XX_TINT34_1] = 7,
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[IRQ_DA8XX_UARTINT0] = 7,
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[IRQ_DA8XX_KEYMGRINT] = 7,
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[IRQ_DA8XX_SECINT] = 7,
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[IRQ_DA8XX_SECKEYERR] = 7,
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[IRQ_DA850_MPUADDRERR0] = 7,
|
|
[IRQ_DA850_MPUPROTERR0] = 7,
|
|
[IRQ_DA850_IOPUADDRERR0] = 7,
|
|
[IRQ_DA850_IOPUPROTERR0] = 7,
|
|
[IRQ_DA850_IOPUADDRERR1] = 7,
|
|
[IRQ_DA850_IOPUPROTERR1] = 7,
|
|
[IRQ_DA850_IOPUADDRERR2] = 7,
|
|
[IRQ_DA850_IOPUPROTERR2] = 7,
|
|
[IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
|
|
[IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
|
|
[IRQ_DA850_MPUADDRERR1] = 7,
|
|
[IRQ_DA850_MPUPROTERR1] = 7,
|
|
[IRQ_DA850_IOPUADDRERR3] = 7,
|
|
[IRQ_DA850_IOPUPROTERR3] = 7,
|
|
[IRQ_DA850_IOPUADDRERR4] = 7,
|
|
[IRQ_DA850_IOPUPROTERR4] = 7,
|
|
[IRQ_DA850_IOPUADDRERR5] = 7,
|
|
[IRQ_DA850_IOPUPROTERR5] = 7,
|
|
[IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
|
|
[IRQ_DA8XX_CHIPINT0] = 7,
|
|
[IRQ_DA8XX_CHIPINT1] = 7,
|
|
[IRQ_DA8XX_CHIPINT2] = 7,
|
|
[IRQ_DA8XX_CHIPINT3] = 7,
|
|
[IRQ_DA8XX_TCERRINT1] = 7,
|
|
[IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
|
|
[IRQ_DA8XX_C0_RX_PULSE] = 7,
|
|
[IRQ_DA8XX_C0_TX_PULSE] = 7,
|
|
[IRQ_DA8XX_C0_MISC_PULSE] = 7,
|
|
[IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
|
|
[IRQ_DA8XX_C1_RX_PULSE] = 7,
|
|
[IRQ_DA8XX_C1_TX_PULSE] = 7,
|
|
[IRQ_DA8XX_C1_MISC_PULSE] = 7,
|
|
[IRQ_DA8XX_MEMERR] = 7,
|
|
[IRQ_DA8XX_GPIO0] = 7,
|
|
[IRQ_DA8XX_GPIO1] = 7,
|
|
[IRQ_DA8XX_GPIO2] = 7,
|
|
[IRQ_DA8XX_GPIO3] = 7,
|
|
[IRQ_DA8XX_GPIO4] = 7,
|
|
[IRQ_DA8XX_GPIO5] = 7,
|
|
[IRQ_DA8XX_GPIO6] = 7,
|
|
[IRQ_DA8XX_GPIO7] = 7,
|
|
[IRQ_DA8XX_GPIO8] = 7,
|
|
[IRQ_DA8XX_I2CINT1] = 7,
|
|
[IRQ_DA8XX_LCDINT] = 7,
|
|
[IRQ_DA8XX_UARTINT1] = 7,
|
|
[IRQ_DA8XX_MCASPINT] = 7,
|
|
[IRQ_DA8XX_ALLINT1] = 7,
|
|
[IRQ_DA8XX_SPINT1] = 7,
|
|
[IRQ_DA8XX_UHPI_INT1] = 7,
|
|
[IRQ_DA8XX_USB_INT] = 7,
|
|
[IRQ_DA8XX_IRQN] = 7,
|
|
[IRQ_DA8XX_RWAKEUP] = 7,
|
|
[IRQ_DA8XX_UARTINT2] = 7,
|
|
[IRQ_DA8XX_DFTSSINT] = 7,
|
|
[IRQ_DA8XX_EHRPWM0] = 7,
|
|
[IRQ_DA8XX_EHRPWM0TZ] = 7,
|
|
[IRQ_DA8XX_EHRPWM1] = 7,
|
|
[IRQ_DA8XX_EHRPWM1TZ] = 7,
|
|
[IRQ_DA850_SATAINT] = 7,
|
|
[IRQ_DA850_TINT12_2] = 7,
|
|
[IRQ_DA850_TINT34_2] = 7,
|
|
[IRQ_DA850_TINTALL_2] = 7,
|
|
[IRQ_DA8XX_ECAP0] = 7,
|
|
[IRQ_DA8XX_ECAP1] = 7,
|
|
[IRQ_DA8XX_ECAP2] = 7,
|
|
[IRQ_DA850_MMCSDINT0_1] = 7,
|
|
[IRQ_DA850_MMCSDINT1_1] = 7,
|
|
[IRQ_DA850_T12CMPINT0_2] = 7,
|
|
[IRQ_DA850_T12CMPINT1_2] = 7,
|
|
[IRQ_DA850_T12CMPINT2_2] = 7,
|
|
[IRQ_DA850_T12CMPINT3_2] = 7,
|
|
[IRQ_DA850_T12CMPINT4_2] = 7,
|
|
[IRQ_DA850_T12CMPINT5_2] = 7,
|
|
[IRQ_DA850_T12CMPINT6_2] = 7,
|
|
[IRQ_DA850_T12CMPINT7_2] = 7,
|
|
[IRQ_DA850_T12CMPINT0_3] = 7,
|
|
[IRQ_DA850_T12CMPINT1_3] = 7,
|
|
[IRQ_DA850_T12CMPINT2_3] = 7,
|
|
[IRQ_DA850_T12CMPINT3_3] = 7,
|
|
[IRQ_DA850_T12CMPINT4_3] = 7,
|
|
[IRQ_DA850_T12CMPINT5_3] = 7,
|
|
[IRQ_DA850_T12CMPINT6_3] = 7,
|
|
[IRQ_DA850_T12CMPINT7_3] = 7,
|
|
[IRQ_DA850_RPIINT] = 7,
|
|
[IRQ_DA850_VPIFINT] = 7,
|
|
[IRQ_DA850_CCINT1] = 7,
|
|
[IRQ_DA850_CCERRINT1] = 7,
|
|
[IRQ_DA850_TCERRINT2] = 7,
|
|
[IRQ_DA850_TINT12_3] = 7,
|
|
[IRQ_DA850_TINT34_3] = 7,
|
|
[IRQ_DA850_TINTALL_3] = 7,
|
|
[IRQ_DA850_MCBSP0RINT] = 7,
|
|
[IRQ_DA850_MCBSP0XINT] = 7,
|
|
[IRQ_DA850_MCBSP1RINT] = 7,
|
|
[IRQ_DA850_MCBSP1XINT] = 7,
|
|
[IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
|
|
};
|
|
|
|
static struct map_desc da850_io_desc[] = {
|
|
{
|
|
.virtual = IO_VIRT,
|
|
.pfn = __phys_to_pfn(IO_PHYS),
|
|
.length = IO_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = DA8XX_CP_INTC_VIRT,
|
|
.pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
|
|
.length = DA8XX_CP_INTC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
static void __iomem *da850_psc_bases[] = {
|
|
IO_ADDRESS(DA8XX_PSC0_BASE),
|
|
IO_ADDRESS(DA8XX_PSC1_BASE),
|
|
};
|
|
|
|
/* Contents of JTAG ID register used to identify exact cpu type */
|
|
static struct davinci_id da850_ids[] = {
|
|
{
|
|
.variant = 0x0,
|
|
.part_no = 0xb7d1,
|
|
.manufacturer = 0x017, /* 0x02f >> 1 */
|
|
.cpu_id = DAVINCI_CPU_ID_DA850,
|
|
.name = "da850/omap-l138",
|
|
},
|
|
};
|
|
|
|
static struct davinci_timer_instance da850_timer_instance[4] = {
|
|
{
|
|
.base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
|
|
.bottom_irq = IRQ_DA8XX_TINT12_0,
|
|
.top_irq = IRQ_DA8XX_TINT34_0,
|
|
},
|
|
{
|
|
.base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
|
|
.bottom_irq = IRQ_DA8XX_TINT12_1,
|
|
.top_irq = IRQ_DA8XX_TINT34_1,
|
|
},
|
|
{
|
|
.base = IO_ADDRESS(DA850_TIMER64P2_BASE),
|
|
.bottom_irq = IRQ_DA850_TINT12_2,
|
|
.top_irq = IRQ_DA850_TINT34_2,
|
|
},
|
|
{
|
|
.base = IO_ADDRESS(DA850_TIMER64P3_BASE),
|
|
.bottom_irq = IRQ_DA850_TINT12_3,
|
|
.top_irq = IRQ_DA850_TINT34_3,
|
|
},
|
|
};
|
|
|
|
/*
|
|
* T0_BOT: Timer 0, bottom : Used for clock_event
|
|
* T0_TOP: Timer 0, top : Used for clocksource
|
|
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
|
|
*/
|
|
static struct davinci_timer_info da850_timer_info = {
|
|
.timers = da850_timer_instance,
|
|
.clockevent_id = T0_BOT,
|
|
.clocksource_id = T0_TOP,
|
|
};
|
|
|
|
static struct davinci_soc_info davinci_soc_info_da850 = {
|
|
.io_desc = da850_io_desc,
|
|
.io_desc_num = ARRAY_SIZE(da850_io_desc),
|
|
.jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
|
|
.ids = da850_ids,
|
|
.ids_num = ARRAY_SIZE(da850_ids),
|
|
.cpu_clks = da850_clks,
|
|
.psc_bases = da850_psc_bases,
|
|
.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
|
|
.pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
|
|
.pinmux_pins = da850_pins,
|
|
.pinmux_pins_num = ARRAY_SIZE(da850_pins),
|
|
.intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
|
|
.intc_type = DAVINCI_INTC_TYPE_CP_INTC,
|
|
.intc_irq_prios = da850_default_priorities,
|
|
.intc_irq_num = DA850_N_CP_INTC_IRQ,
|
|
.timer_info = &da850_timer_info,
|
|
.gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
|
|
.gpio_num = 144,
|
|
.gpio_irq = IRQ_DA8XX_GPIO0,
|
|
.serial_dev = &da8xx_serial_device,
|
|
.emac_pdata = &da8xx_emac_pdata,
|
|
};
|
|
|
|
void __init da850_init(void)
|
|
{
|
|
davinci_common_init(&davinci_soc_info_da850);
|
|
}
|