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Add support for EDAC on the Aspeed AST2500 SoC. Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Cc: Joel Stanley <joel@jms.id.au> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: https://lkml.kernel.org/r/1547743097-5236-3-git-send-email-schaecsn@gmx.net
26 lines
747 B
Plaintext
26 lines
747 B
Plaintext
Aspeed AST2500 SoC EDAC node
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The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
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correction check).
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The memory controller supports SECDED (single bit error correction, double bit
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error detection) and single bit error auto scrubbing by reserving 8 bits for
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every 64 bit word (effectively reducing available memory to 8/9).
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Note, the bootloader must configure ECC mode in the memory controller.
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Required properties:
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- compatible: should be "aspeed,ast2500-sdram-edac"
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- reg: sdram controller register set should be <0x1e6e0000 0x174>
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- interrupts: should be AVIC interrupt #0
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Example:
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edac: sdram@1e6e0000 {
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compatible = "aspeed,ast2500-sdram-edac";
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reg = <0x1e6e0000 0x174>;
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interrupts = <0>;
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};
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