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4848229494
The initialization function for the J-Core AIC aic_irq_of_init() is
currently missing the call to irq_alloc_descs() which allocates and
initializes all the IRQ descriptors. Add missing function call and
return the error code from irq_alloc_descs() in case the allocation
fails.
Fixes: 981b58f66c ("irqchip/jcore-aic: Add J-Core AIC driver")
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Tested-by: Rob Landley <rob@landley.net>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230510163343.43090-1-glaubitz@physik.fu-berlin.de
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/*
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* J-Core SoC AIC driver
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*
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* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/cpu.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define JCORE_AIC_MAX_HWIRQ 127
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#define JCORE_AIC1_MIN_HWIRQ 16
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#define JCORE_AIC2_MIN_HWIRQ 64
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#define JCORE_AIC1_INTPRI_REG 8
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static struct irq_chip jcore_aic;
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/*
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* The J-Core AIC1 and AIC2 are cpu-local interrupt controllers and do
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* not distinguish or use distinct irq number ranges for per-cpu event
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* interrupts (timer, IPI). Since information to determine whether a
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* particular irq number should be treated as per-cpu is not available
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* at mapping time, we use a wrapper handler function which chooses
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* the right handler at runtime based on whether IRQF_PERCPU was used
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* when requesting the irq.
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*/
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static void handle_jcore_irq(struct irq_desc *desc)
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{
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if (irqd_is_per_cpu(irq_desc_get_irq_data(desc)))
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handle_percpu_irq(desc);
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else
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handle_simple_irq(desc);
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}
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static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct irq_chip *aic = d->host_data;
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irq_set_chip_and_handler(irq, aic, handle_jcore_irq);
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return 0;
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}
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static const struct irq_domain_ops jcore_aic_irqdomain_ops = {
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.map = jcore_aic_irqdomain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static void noop(struct irq_data *data)
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{
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}
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static int __init aic_irq_of_init(struct device_node *node,
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struct device_node *parent)
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{
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unsigned min_irq = JCORE_AIC2_MIN_HWIRQ;
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unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1;
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struct irq_domain *domain;
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int ret;
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pr_info("Initializing J-Core AIC\n");
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/* AIC1 needs priority initialization to receive interrupts. */
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if (of_device_is_compatible(node, "jcore,aic1")) {
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unsigned cpu;
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for_each_present_cpu(cpu) {
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void __iomem *base = of_iomap(node, cpu);
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if (!base) {
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pr_err("Unable to map AIC for cpu %u\n", cpu);
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return -ENOMEM;
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}
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__raw_writel(0xffffffff, base + JCORE_AIC1_INTPRI_REG);
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iounmap(base);
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}
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min_irq = JCORE_AIC1_MIN_HWIRQ;
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}
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/*
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* The irq chip framework requires either mask/unmask or enable/disable
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* function pointers to be provided, but the hardware does not have any
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* such mechanism; the only interrupt masking is at the cpu level and
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* it affects all interrupts. We provide dummy mask/unmask. The hardware
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* handles all interrupt control and clears pending status when the cpu
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* accepts the interrupt.
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*/
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jcore_aic.irq_mask = noop;
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jcore_aic.irq_unmask = noop;
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jcore_aic.name = "AIC";
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ret = irq_alloc_descs(-1, min_irq, dom_sz - min_irq,
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of_node_to_nid(node));
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if (ret < 0)
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return ret;
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domain = irq_domain_add_legacy(node, dom_sz - min_irq, min_irq, min_irq,
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&jcore_aic_irqdomain_ops,
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&jcore_aic);
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if (!domain)
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return -ENOMEM;
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return 0;
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}
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IRQCHIP_DECLARE(jcore_aic2, "jcore,aic2", aic_irq_of_init);
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IRQCHIP_DECLARE(jcore_aic1, "jcore,aic1", aic_irq_of_init);
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