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c1bfa985de
All of the keystone devices have a separate register to hold post divider value for main pll clock. Currently the fixed-postdiv value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to use a value of 2 for this. Now that we have fixed this in the pll clock driver change the dt bindings for the same. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
267 lines
6.5 KiB
Plaintext
267 lines
6.5 KiB
Plaintext
/*
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* Copyright 2013-2014 Texas Instruments, Inc.
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*
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* Keystone 2 lamarr SoC clock nodes
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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clocks {
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armpllclk: armpllclk@2620370 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclksys>;
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clock-output-names = "arm-pll-clk";
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reg = <0x02620370 4>;
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reg-names = "control";
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};
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mainpllclk: mainpllclk@2310110 {
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#clock-cells = <0>;
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compatible = "ti,keystone,main-pll-clock";
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clocks = <&refclksys>;
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reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
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reg-names = "control", "multiplier", "post-divider";
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};
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papllclk: papllclk@2620358 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclksys>;
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clock-output-names = "papllclk";
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reg = <0x02620358 4>;
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reg-names = "control";
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};
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ddr3apllclk: ddr3apllclk@2620360 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclksys>;
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clock-output-names = "ddr-3a-pll-clk";
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reg = <0x02620360 4>;
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reg-names = "control";
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};
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clkdfeiqnsys: clkdfeiqnsys {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "dfe";
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reg-names = "control", "domain";
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reg = <0x02350004 0xb00>, <0x02350000 0x400>;
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domain-id = <0>;
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};
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clkpcie1: clkpcie1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "pcie";
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reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <4>;
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};
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clkgem1: clkgem1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem1";
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reg = <0x02350040 0xb00>, <0x02350024 0x400>;
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reg-names = "control", "domain";
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domain-id = <9>;
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};
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clkgem2: clkgem2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem2";
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reg = <0x02350044 0xb00>, <0x02350028 0x400>;
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reg-names = "control", "domain";
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domain-id = <10>;
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};
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clkgem3: clkgem3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem3";
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reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
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reg-names = "control", "domain";
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domain-id = <11>;
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};
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clktac: clktac {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tac";
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reg = <0x02350064 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <17>;
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};
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clkrac: clkrac {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "rac";
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reg = <0x02350068 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <17>;
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};
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clkdfepd0: clkdfepd0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "dfe-pd0";
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reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <18>;
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};
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clkfftc0: clkfftc0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-0";
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reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
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reg-names = "control", "domain";
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domain-id = <19>;
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};
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clkosr: clkosr {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "osr";
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reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
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reg-names = "control", "domain";
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domain-id = <21>;
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};
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clktcp3d0: clktcp3d0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tcp3d-0";
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reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
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reg-names = "control", "domain";
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domain-id = <22>;
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};
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clktcp3d1: clktcp3d1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tcp3d-1";
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reg = <0x02350094 0xb00>, <0x02350058 0x400>;
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reg-names = "control", "domain";
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domain-id = <23>;
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};
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clkvcp0: clkvcp0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-0";
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reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkvcp1: clkvcp1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-1";
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reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkvcp2: clkvcp2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-2";
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reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkvcp3: clkvcp3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-3";
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reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkbcp: clkbcp {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "bcp";
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reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
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reg-names = "control", "domain";
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domain-id = <26>;
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};
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clkdfepd1: clkdfepd1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "dfe-pd1";
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reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <27>;
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};
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clkfftc1: clkfftc1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-1";
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reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
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reg-names = "control", "domain";
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domain-id = <28>;
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};
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clkiqnail: clkiqnail {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "iqn-ail";
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reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
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reg-names = "control", "domain";
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domain-id = <29>;
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};
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clkuart2: clkuart2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&clkmodrst0>;
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clock-output-names = "uart2";
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reg = <0x02350000 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clkuart3: clkuart3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&clkmodrst0>;
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clock-output-names = "uart3";
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reg = <0x02350000 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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};
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