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The arm64 module PLT code allocates all PLT entries in a single core section, since the overhead of having a separate init PLT section is not justified by the small number of PLT entries usually required for init code. However, the core and init module regions are allocated independently, and there is a corner case where the core region may be allocated from the VMALLOC region if the dedicated module region is exhausted, but the init region, being much smaller, can still be allocated from the module region. This leads to relocation failures if the distance between those regions exceeds 128 MB. (In fact, this corner case is highly unlikely to occur on arm64, but the issue has been observed on ARM, whose module region is much smaller). So split the core and init PLT regions, and name the latter ".init.plt" so it gets allocated along with (and sufficiently close to) the .init sections that it serves. Also, given that init PLT entries may need to be emitted for branches that target the core module, modify the logic that disregards defined symbols to only disregard symbols that are defined in the same section as the relocated branch instruction. Since there may now be two PLT entries associated with each entry in the symbol table, we can no longer hijack the symbol::st_size fields to record the addresses of PLT entries as we emit them for zero-addend relocations. So instead, perform an explicit comparison to check for duplicate entries. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
220 lines
6.8 KiB
C
220 lines
6.8 KiB
C
/*
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* Copyright (C) 2014-2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/elf.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sort.h>
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struct plt_entry {
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/*
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* A program that conforms to the AArch64 Procedure Call Standard
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* (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
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* IP1 (x17) may be inserted at any branch instruction that is
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* exposed to a relocation that supports long branches. Since that
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* is exactly what we are dealing with here, we are free to use x16
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* as a scratch register in the PLT veneers.
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*/
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__le32 mov0; /* movn x16, #0x.... */
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__le32 mov1; /* movk x16, #0x...., lsl #16 */
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__le32 mov2; /* movk x16, #0x...., lsl #32 */
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__le32 br; /* br x16 */
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};
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static bool in_init(const struct module *mod, void *loc)
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{
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return (u64)loc - (u64)mod->init_layout.base < mod->init_layout.size;
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}
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u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela,
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Elf64_Sym *sym)
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{
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struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
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&mod->arch.init;
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struct plt_entry *plt = (struct plt_entry *)pltsec->plt->sh_addr;
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int i = pltsec->plt_num_entries;
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u64 val = sym->st_value + rela->r_addend;
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/*
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* MOVK/MOVN/MOVZ opcode:
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* +--------+------------+--------+-----------+-------------+---------+
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* | sf[31] | opc[30:29] | 100101 | hw[22:21] | imm16[20:5] | Rd[4:0] |
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* +--------+------------+--------+-----------+-------------+---------+
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*
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* Rd := 0x10 (x16)
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* hw := 0b00 (no shift), 0b01 (lsl #16), 0b10 (lsl #32)
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* opc := 0b11 (MOVK), 0b00 (MOVN), 0b10 (MOVZ)
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* sf := 1 (64-bit variant)
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*/
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plt[i] = (struct plt_entry){
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cpu_to_le32(0x92800010 | (((~val ) & 0xffff)) << 5),
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cpu_to_le32(0xf2a00010 | ((( val >> 16) & 0xffff)) << 5),
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cpu_to_le32(0xf2c00010 | ((( val >> 32) & 0xffff)) << 5),
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cpu_to_le32(0xd61f0200)
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};
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/*
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* Check if the entry we just created is a duplicate. Given that the
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* relocations are sorted, this will be the last entry we allocated.
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* (if one exists).
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*/
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if (i > 0 &&
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plt[i].mov0 == plt[i - 1].mov0 &&
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plt[i].mov1 == plt[i - 1].mov1 &&
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plt[i].mov2 == plt[i - 1].mov2)
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return (u64)&plt[i - 1];
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pltsec->plt_num_entries++;
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BUG_ON(pltsec->plt_num_entries > pltsec->plt_max_entries);
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return (u64)&plt[i];
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}
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#define cmp_3way(a,b) ((a) < (b) ? -1 : (a) > (b))
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static int cmp_rela(const void *a, const void *b)
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{
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const Elf64_Rela *x = a, *y = b;
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int i;
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/* sort by type, symbol index and addend */
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i = cmp_3way(ELF64_R_TYPE(x->r_info), ELF64_R_TYPE(y->r_info));
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if (i == 0)
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i = cmp_3way(ELF64_R_SYM(x->r_info), ELF64_R_SYM(y->r_info));
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if (i == 0)
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i = cmp_3way(x->r_addend, y->r_addend);
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return i;
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}
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static bool duplicate_rel(const Elf64_Rela *rela, int num)
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{
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/*
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* Entries are sorted by type, symbol index and addend. That means
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* that, if a duplicate entry exists, it must be in the preceding
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* slot.
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*/
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return num > 0 && cmp_rela(rela + num, rela + num - 1) == 0;
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}
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static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
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Elf64_Word dstidx)
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{
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unsigned int ret = 0;
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Elf64_Sym *s;
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int i;
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for (i = 0; i < num; i++) {
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switch (ELF64_R_TYPE(rela[i].r_info)) {
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case R_AARCH64_JUMP26:
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case R_AARCH64_CALL26:
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/*
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* We only have to consider branch targets that resolve
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* to symbols that are defined in a different section.
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* This is not simply a heuristic, it is a fundamental
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* limitation, since there is no guaranteed way to emit
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* PLT entries sufficiently close to the branch if the
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* section size exceeds the range of a branch
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* instruction. So ignore relocations against defined
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* symbols if they live in the same section as the
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* relocation target.
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*/
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s = syms + ELF64_R_SYM(rela[i].r_info);
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if (s->st_shndx == dstidx)
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break;
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/*
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* Jump relocations with non-zero addends against
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* undefined symbols are supported by the ELF spec, but
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* do not occur in practice (e.g., 'jump n bytes past
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* the entry point of undefined function symbol f').
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* So we need to support them, but there is no need to
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* take them into consideration when trying to optimize
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* this code. So let's only check for duplicates when
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* the addend is zero: this allows us to record the PLT
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* entry address in the symbol table itself, rather than
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* having to search the list for duplicates each time we
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* emit one.
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*/
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if (rela[i].r_addend != 0 || !duplicate_rel(rela, i))
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ret++;
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break;
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}
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}
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return ret;
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}
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int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
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char *secstrings, struct module *mod)
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{
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unsigned long core_plts = 0;
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unsigned long init_plts = 0;
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Elf64_Sym *syms = NULL;
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int i;
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/*
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* Find the empty .plt section so we can expand it to store the PLT
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* entries. Record the symtab address as well.
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*/
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for (i = 0; i < ehdr->e_shnum; i++) {
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if (!strcmp(secstrings + sechdrs[i].sh_name, ".plt"))
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mod->arch.core.plt = sechdrs + i;
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else if (!strcmp(secstrings + sechdrs[i].sh_name, ".init.plt"))
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mod->arch.init.plt = sechdrs + i;
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else if (sechdrs[i].sh_type == SHT_SYMTAB)
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syms = (Elf64_Sym *)sechdrs[i].sh_addr;
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}
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if (!mod->arch.core.plt || !mod->arch.init.plt) {
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pr_err("%s: module PLT section(s) missing\n", mod->name);
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return -ENOEXEC;
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}
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if (!syms) {
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pr_err("%s: module symtab section missing\n", mod->name);
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return -ENOEXEC;
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}
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for (i = 0; i < ehdr->e_shnum; i++) {
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Elf64_Rela *rels = (void *)ehdr + sechdrs[i].sh_offset;
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int numrels = sechdrs[i].sh_size / sizeof(Elf64_Rela);
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Elf64_Shdr *dstsec = sechdrs + sechdrs[i].sh_info;
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if (sechdrs[i].sh_type != SHT_RELA)
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continue;
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/* ignore relocations that operate on non-exec sections */
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if (!(dstsec->sh_flags & SHF_EXECINSTR))
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continue;
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/* sort by type, symbol index and addend */
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sort(rels, numrels, sizeof(Elf64_Rela), cmp_rela, NULL);
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if (strncmp(secstrings + dstsec->sh_name, ".init", 5) != 0)
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core_plts += count_plts(syms, rels, numrels,
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sechdrs[i].sh_info);
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else
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init_plts += count_plts(syms, rels, numrels,
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sechdrs[i].sh_info);
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}
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mod->arch.core.plt->sh_type = SHT_NOBITS;
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mod->arch.core.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
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mod->arch.core.plt->sh_addralign = L1_CACHE_BYTES;
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mod->arch.core.plt->sh_size = (core_plts + 1) * sizeof(struct plt_entry);
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mod->arch.core.plt_num_entries = 0;
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mod->arch.core.plt_max_entries = core_plts;
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mod->arch.init.plt->sh_type = SHT_NOBITS;
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mod->arch.init.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
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mod->arch.init.plt->sh_addralign = L1_CACHE_BYTES;
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mod->arch.init.plt->sh_size = (init_plts + 1) * sizeof(struct plt_entry);
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mod->arch.init.plt_num_entries = 0;
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mod->arch.init.plt_max_entries = init_plts;
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return 0;
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}
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