Michal Simek 598acab44d microblaze: Define correct L1_CACHE_SHIFT value ... Microblaze cacheline length is configurable and current cpu uses two cacheline length 4 and 8. We are taking conservative maximum value to be sure that cacheline alignment is satisfied for all cases. Here is the calculation for cacheline lenght 8 32bit=4Byte values which is corresponding with SHIFT 5. Signed-off-by: Michal Simek <monstr@monstr.eu>		2010-05-06 11:21:59 +02:00
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boot	microblaze: Makefile cleanups	2010-04-01 08:38:19 +02:00
configs	microblaze: Defconfig update	2010-02-03 10:18:20 +01:00
include/asm	microblaze: Define correct L1_CACHE_SHIFT value	2010-05-06 11:21:59 +02:00
kernel	microblaze: cpuinfo shows cache line length	2010-05-06 11:21:59 +02:00
lib	microblaze: Support word copying in copy_tofrom_user	2010-04-01 08:38:25 +02:00
mm	microblaze: Fix consistent code	2010-05-06 11:21:59 +02:00
oprofile	microblaze: Core oprofile configs and hooks	2009-12-14 08:45:07 +01:00
pci	microblaze: resource/PCI: align functions now return start of resource	2010-05-06 11:21:57 +02:00
platform	microblaze: Use lowest-common-denominator default CPU settings	2009-12-14 08:45:02 +01:00
Kconfig	microblaze: Kconfig Fix - pci	2010-04-01 08:38:24 +02:00
Kconfig.debug	microblaze: Add TRACE_IRQFLAGS_SUPPORT	2009-12-14 08:40:09 +01:00
Makefile	microblaze: Fix Makefile to delete build generated files	2010-04-01 08:38:19 +02:00