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d3eabf2f2c
The CMO op macros initially used lower case, as the original iteration
of the ALT_CMO_OP alternative stringified the first parameter to
finalise the assembly for the standard variant.
As a knock-on, the T-Head versions of these CMOs had to use mixed case
defines. Commit dd23e95358 ("RISC-V: replace cbom instructions with
an insn-def") removed the asm construction with stringify, replacing it
an insn-def macro, rending the lower-case surplus to requirements.
As far as I can tell from a brief check, CBO_zero does not see similar
use and didn't require the mixed case define in the first place.
Replace the lower case characters now for consistency with other
insn-def macros in the standard and T-Head forms, and adjust the
callsites.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20230915-aloe-dollar-994937477776@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
35 lines
836 B
C
35 lines
836 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*/
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#include <linux/export.h>
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#include <linux/libnvdimm.h>
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#include <asm/cacheflush.h>
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#include <asm/dma-noncoherent.h>
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void arch_wb_cache_pmem(void *addr, size_t size)
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{
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#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
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if (unlikely(noncoherent_cache_ops.wback)) {
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noncoherent_cache_ops.wback(virt_to_phys(addr), size);
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return;
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}
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#endif
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ALT_CMO_OP(CLEAN, addr, size, riscv_cbom_block_size);
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}
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EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
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void arch_invalidate_pmem(void *addr, size_t size)
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{
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#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
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if (unlikely(noncoherent_cache_ops.inv)) {
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noncoherent_cache_ops.inv(virt_to_phys(addr), size);
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return;
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}
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#endif
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ALT_CMO_OP(INVAL, addr, size, riscv_cbom_block_size);
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}
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EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
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