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7c43d54728
On OMAP4 platform the iclk control is completly under hardware control and no software control is available. This difference w.r.t previous OMAP's needs all the common driver accross OMAP's , cpu_is_xxxx() checks. To avoid poulluting the drivers dummy clock nodes are created (The autogeneration script has been updated accordingly). Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: made OMAP1 dummy_ck common and edited patch to reuse that] Signed-off-by: Paul Walmsley <paul@pwsan.com>
211 lines
6.9 KiB
C
211 lines
6.9 KiB
C
/*
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* OMAP clock: data structure definitions, function prototypes, shared macros
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*
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* Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_OMAP_CLOCK_H
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#define __ARCH_ARM_OMAP_CLOCK_H
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#include <linux/list.h>
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struct module;
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struct clk;
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struct clockdomain;
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struct clkops {
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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void (*find_idlest)(struct clk *, void __iomem **,
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u8 *, u8 *);
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void (*find_companion)(struct clk *, void __iomem **,
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u8 *);
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};
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#ifdef CONFIG_ARCH_OMAP2PLUS
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struct clksel_rate {
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u32 val;
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u8 div;
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u8 flags;
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};
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struct clksel {
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struct clk *parent;
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const struct clksel_rate *rates;
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};
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/**
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* struct dpll_data - DPLL registers and integration data
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* @mult_div1_reg: register containing the DPLL M and N bitfields
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* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
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* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
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* @clk_bypass: struct clk pointer to the clock's bypass clock input
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* @clk_ref: struct clk pointer to the clock's reference clock input
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* @control_reg: register containing the DPLL mode bitfield
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* @enable_mask: mask of the DPLL mode bitfield in @control_reg
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* @rate_tolerance: maximum variance allowed from target rate (in Hz)
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* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
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* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
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* @max_multiplier: maximum valid non-bypass multiplier value (actual)
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* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
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* @min_divider: minimum valid non-bypass divider value (actual)
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* @max_divider: maximum valid non-bypass divider value (actual)
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* @modes: possible values of @enable_mask
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* @autoidle_reg: register containing the DPLL autoidle mode bitfield
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* @idlest_reg: register containing the DPLL idle status bitfield
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* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
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* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
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* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
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* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
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* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
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* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
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* @flags: DPLL type/features (see below)
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*
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* Possible values for @flags:
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* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
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* NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
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* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
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*
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* XXX Some DPLLs have multiple bypass inputs, so it's not technically
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* correct to only have one @clk_bypass pointer.
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*
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* XXX @rate_tolerance should probably be deprecated - currently there
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* don't seem to be any usecases for DPLL rounding that is not exact.
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*
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* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
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* @last_rounded_n) should be separated from the runtime-fixed fields
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* and placed into a differenct structure, so that the runtime-fixed data
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* can be placed into read-only space.
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*/
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struct dpll_data {
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void __iomem *mult_div1_reg;
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u32 mult_mask;
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u32 div1_mask;
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struct clk *clk_bypass;
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struct clk *clk_ref;
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void __iomem *control_reg;
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u32 enable_mask;
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unsigned int rate_tolerance;
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unsigned long last_rounded_rate;
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u16 last_rounded_m;
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u16 max_multiplier;
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u8 last_rounded_n;
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u8 min_divider;
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u8 max_divider;
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u8 modes;
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#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
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void __iomem *autoidle_reg;
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void __iomem *idlest_reg;
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u32 autoidle_mask;
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u32 freqsel_mask;
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u32 idlest_mask;
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u8 auto_recal_bit;
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u8 recal_en_bit;
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u8 recal_st_bit;
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u8 flags;
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# endif
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};
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#endif
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struct clk {
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struct list_head node;
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const struct clkops *ops;
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const char *name;
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struct clk *parent;
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struct list_head children;
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struct list_head sibling; /* node for children */
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unsigned long rate;
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void __iomem *enable_reg;
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unsigned long (*recalc)(struct clk *);
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int (*set_rate)(struct clk *, unsigned long);
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long (*round_rate)(struct clk *, unsigned long);
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void (*init)(struct clk *);
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__u8 enable_bit;
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__s8 usecount;
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u8 fixed_div;
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u8 flags;
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#ifdef CONFIG_ARCH_OMAP2PLUS
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void __iomem *clksel_reg;
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u32 clksel_mask;
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const struct clksel *clksel;
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struct dpll_data *dpll_data;
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const char *clkdm_name;
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struct clockdomain *clkdm;
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#else
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__u8 rate_offset;
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__u8 src_offset;
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#endif
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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struct dentry *dent; /* For visible tree hierarchy */
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#endif
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};
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struct cpufreq_frequency_table;
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struct clk_functions {
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int (*clk_enable)(struct clk *clk);
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void (*clk_disable)(struct clk *clk);
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long (*clk_round_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_rate)(struct clk *clk, unsigned long rate);
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int (*clk_set_parent)(struct clk *clk, struct clk *parent);
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void (*clk_allow_idle)(struct clk *clk);
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void (*clk_deny_idle)(struct clk *clk);
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void (*clk_disable_unused)(struct clk *clk);
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#ifdef CONFIG_CPU_FREQ
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void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
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void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
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#endif
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};
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extern int mpurate;
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extern int clk_init(struct clk_functions *custom_clocks);
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extern void clk_preinit(struct clk *clk);
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extern int clk_register(struct clk *clk);
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extern void clk_reparent(struct clk *child, struct clk *parent);
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extern void clk_unregister(struct clk *clk);
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extern void propagate_rate(struct clk *clk);
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extern void recalculate_root_clocks(void);
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extern unsigned long followparent_recalc(struct clk *clk);
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extern void clk_enable_init_clocks(void);
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unsigned long omap_fixed_divisor_recalc(struct clk *clk);
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#ifdef CONFIG_CPU_FREQ
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extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
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extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
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#endif
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extern struct clk *omap_clk_get_by_name(const char *name);
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extern const struct clkops clkops_null;
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extern struct clk dummy_ck;
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/* Clock flags */
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
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#define CLOCK_IDLE_CONTROL (1 << 1)
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#define CLOCK_NO_IDLE_PARENT (1 << 2)
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#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
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#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
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/* Clksel_rate flags */
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#define DEFAULT_RATE (1 << 0)
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#define RATE_IN_242X (1 << 1)
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#define RATE_IN_243X (1 << 2)
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#define RATE_IN_343X (1 << 3) /* rates common to all 343X */
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#define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
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#define RATE_IN_36XX (1 << 5)
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#define RATE_IN_4430 (1 << 6)
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
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#endif
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