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Most of things are in place and we can enable support for 5-level paging. The patch makes XEN_PV and XEN_PVH dependent on !X86_5LEVEL. Both are not ready to work with 5-level paging. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Reviewed-by: Juergen Gross <jgross@suse.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arch@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20170716225954.74185-9-kirill.shutemov@linux.intel.com [ Minor readability edits. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
65 lines
2.5 KiB
Plaintext
65 lines
2.5 KiB
Plaintext
== Overview ==
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Original x86-64 was limited by 4-level paing to 256 TiB of virtual address
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space and 64 TiB of physical address space. We are already bumping into
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this limit: some vendors offers servers with 64 TiB of memory today.
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To overcome the limitation upcoming hardware will introduce support for
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5-level paging. It is a straight-forward extension of the current page
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table structure adding one more layer of translation.
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It bumps the limits to 128 PiB of virtual address space and 4 PiB of
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physical address space. This "ought to be enough for anybody" ©.
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QEMU 2.9 and later support 5-level paging.
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Virtual memory layout for 5-level paging is described in
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Documentation/x86/x86_64/mm.txt
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== Enabling 5-level paging ==
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CONFIG_X86_5LEVEL=y enables the feature.
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So far, a kernel compiled with the option enabled will be able to boot
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only on machines that supports the feature -- see for 'la57' flag in
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/proc/cpuinfo.
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The plan is to implement boot-time switching between 4- and 5-level paging
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in the future.
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== User-space and large virtual address space ==
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On x86, 5-level paging enables 56-bit userspace virtual address space.
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Not all user space is ready to handle wide addresses. It's known that
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at least some JIT compilers use higher bits in pointers to encode their
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information. It collides with valid pointers with 5-level paging and
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leads to crashes.
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To mitigate this, we are not going to allocate virtual address space
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above 47-bit by default.
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But userspace can ask for allocation from full address space by
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specifying hint address (with or without MAP_FIXED) above 47-bits.
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If hint address set above 47-bit, but MAP_FIXED is not specified, we try
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to look for unmapped area by specified address. If it's already
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occupied, we look for unmapped area in *full* address space, rather than
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from 47-bit window.
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A high hint address would only affect the allocation in question, but not
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any future mmap()s.
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Specifying high hint address on older kernel or on machine without 5-level
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paging support is safe. The hint will be ignored and kernel will fall back
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to allocation from 47-bit address space.
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This approach helps to easily make application's memory allocator aware
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about large address space without manually tracking allocated virtual
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address space.
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One important case we need to handle here is interaction with MPX.
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MPX (without MAWA extension) cannot handle addresses above 47-bit, so we
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need to make sure that MPX cannot be enabled we already have VMA above
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the boundary and forbid creating such VMAs once MPX is enabled.
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