mirror of
https://github.com/torvalds/linux.git
synced 2024-11-08 21:21:47 +00:00
3edad321b1
Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
54 lines
1.6 KiB
Plaintext
54 lines
1.6 KiB
Plaintext
#
|
|
# Memory devices
|
|
#
|
|
|
|
menuconfig MEMORY
|
|
bool "Memory Controller drivers"
|
|
|
|
if MEMORY
|
|
|
|
config TI_EMIF
|
|
tristate "Texas Instruments EMIF driver"
|
|
depends on ARCH_OMAP2PLUS
|
|
select DDR
|
|
help
|
|
This driver is for the EMIF module available in Texas Instruments
|
|
SoCs. EMIF is an SDRAM controller that, based on its revision,
|
|
supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
|
|
This driver takes care of only LPDDR2 memories presently. The
|
|
functions of the driver includes re-configuring AC timing
|
|
parameters and other settings during frequency, voltage and
|
|
temperature changes
|
|
|
|
config MVEBU_DEVBUS
|
|
bool "Marvell EBU Device Bus Controller"
|
|
default y
|
|
depends on PLAT_ORION && OF
|
|
help
|
|
This driver is for the Device Bus controller available in some
|
|
Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
|
|
Armada 370 and Armada XP. This controller allows to handle flash
|
|
devices such as NOR, NAND, SRAM, and FPGA.
|
|
|
|
config TEGRA20_MC
|
|
bool "Tegra20 Memory Controller(MC) driver"
|
|
default y
|
|
depends on ARCH_TEGRA_2x_SOC
|
|
help
|
|
This driver is for the Memory Controller(MC) module available
|
|
in Tegra20 SoCs, mainly for a address translation fault
|
|
analysis, especially for IOMMU/GART(Graphics Address
|
|
Relocation Table) module.
|
|
|
|
config TEGRA30_MC
|
|
bool "Tegra30 Memory Controller(MC) driver"
|
|
default y
|
|
depends on ARCH_TEGRA_3x_SOC
|
|
help
|
|
This driver is for the Memory Controller(MC) module available
|
|
in Tegra30 SoCs, mainly for a address translation fault
|
|
analysis, especially for IOMMU/SMMU(System Memory Management
|
|
Unit) module.
|
|
|
|
endif
|