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b2b0c60543
F15h "multiplexes" between the configuration space of the two DRAM controllers by toggling D18F1x10C[DctCfgSel] while F10h has a different set of registers for DCT0, and DCT1 in extended PCI config space. Add DCT configuration space accessors per family thus wrapping all the different access prerequisites. Clean up code while at it, shorten names. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
214 lines
5.0 KiB
C
214 lines
5.0 KiB
C
#include "amd64_edac.h"
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static ssize_t amd64_inject_section_show(struct mem_ctl_info *mci, char *buf)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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return sprintf(buf, "0x%x\n", pvt->injection.section);
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}
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/*
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* store error injection section value which refers to one of 4 16-byte sections
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* within a 64-byte cacheline
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*
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* range: 0..3
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*/
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static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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unsigned long value;
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int ret = 0;
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ret = strict_strtoul(data, 10, &value);
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if (ret != -EINVAL) {
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if (value > 3) {
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amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
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return -EINVAL;
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}
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pvt->injection.section = (u32) value;
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return count;
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}
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return ret;
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}
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static ssize_t amd64_inject_word_show(struct mem_ctl_info *mci, char *buf)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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return sprintf(buf, "0x%x\n", pvt->injection.word);
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}
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/*
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* store error injection word value which refers to one of 9 16-bit word of the
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* 16-byte (128-bit + ECC bits) section
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*
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* range: 0..8
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*/
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static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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unsigned long value;
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int ret = 0;
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ret = strict_strtoul(data, 10, &value);
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if (ret != -EINVAL) {
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if (value > 8) {
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amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
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return -EINVAL;
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}
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pvt->injection.word = (u32) value;
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return count;
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}
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return ret;
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}
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static ssize_t amd64_inject_ecc_vector_show(struct mem_ctl_info *mci, char *buf)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
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}
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/*
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* store 16 bit error injection vector which enables injecting errors to the
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* corresponding bit within the error injection word above. When used during a
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* DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
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*/
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static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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unsigned long value;
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int ret = 0;
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ret = strict_strtoul(data, 16, &value);
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if (ret != -EINVAL) {
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if (value & 0xFFFF0000) {
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amd64_warn("%s: invalid EccVector: 0x%lx\n",
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__func__, value);
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return -EINVAL;
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}
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pvt->injection.bit_map = (u32) value;
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return count;
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}
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return ret;
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}
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/*
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* Do a DRAM ECC read. Assemble staged values in the pvt area, format into
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* fields needed by the injection registers and read the NB Array Data Port.
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*/
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static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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unsigned long value;
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u32 section, word_bits;
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int ret = 0;
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ret = strict_strtoul(data, 10, &value);
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if (ret != -EINVAL) {
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/* Form value to choose 16-byte section of cacheline */
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section = F10_NB_ARRAY_DRAM_ECC |
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SET_NB_ARRAY_ADDRESS(pvt->injection.section);
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amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
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word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
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pvt->injection.bit_map);
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/* Issue 'word' and 'bit' along with the READ request */
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amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
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debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
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return count;
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}
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return ret;
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}
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/*
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* Do a DRAM ECC write. Assemble staged values in the pvt area and format into
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* fields needed by the injection registers.
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*/
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static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
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const char *data, size_t count)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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unsigned long value;
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u32 section, word_bits;
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int ret = 0;
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ret = strict_strtoul(data, 10, &value);
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if (ret != -EINVAL) {
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/* Form value to choose 16-byte section of cacheline */
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section = F10_NB_ARRAY_DRAM_ECC |
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SET_NB_ARRAY_ADDRESS(pvt->injection.section);
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amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
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word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
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pvt->injection.bit_map);
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/* Issue 'word' and 'bit' along with the READ request */
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amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
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debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
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return count;
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}
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return ret;
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}
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/*
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* update NUM_INJ_ATTRS in case you add new members
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*/
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struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
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{
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.attr = {
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.name = "inject_section",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = amd64_inject_section_show,
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.store = amd64_inject_section_store,
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},
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{
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.attr = {
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.name = "inject_word",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = amd64_inject_word_show,
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.store = amd64_inject_word_store,
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},
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{
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.attr = {
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.name = "inject_ecc_vector",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = amd64_inject_ecc_vector_show,
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.store = amd64_inject_ecc_vector_store,
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},
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{
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.attr = {
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.name = "inject_write",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = NULL,
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.store = amd64_inject_write_store,
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},
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{
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.attr = {
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.name = "inject_read",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = NULL,
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.store = amd64_inject_read_store,
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},
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};
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