Like Xu 556f3c9ad7 KVM: x86/pmu: Limit the maximum number of supported AMD GP counters ... The AMD PerfMonV2 specification allows for a maximum of 16 GP counters, but currently only 6 pairs of MSRs are accepted by KVM. While AMD64_NUM_COUNTERS_CORE is already equal to 6, increasing without adjusting msrs_to_save_all[] could result in out-of-bounds accesses. Therefore introduce a macro (named KVM_AMD_PMC_MAX_GENERIC) to refer to the number of counters supported by KVM. Signed-off-by: Like Xu <likexu@tencent.com> Reviewed-by: Jim Mattson <jmattson@google.com> Message-Id: <20220919091008.60695-3-likexu@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2022-11-09 12:26:54 -05:00
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asm	KVM: x86/pmu: Limit the maximum number of supported AMD GP counters	2022-11-09 12:26:54 -05:00
uapi/asm	- SGX2 ISA support which makes enclave memory management much more	2022-08-05 10:47:40 -07:00