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054b93e444
The context programs are *very* simple compared to the ones used by the binary driver. There's notes in nv40_grctx.c explaining most of the things we don't implement. If we discover if/why any of it is required further down the track, we'll handle it then. The PGRAPH state generated for each chipset should match what NVIDIA do almost exactly (there's a couple of exceptions). If someone has a lot of time on their hands, they could figure out the mapping of object/method to PGRAPH register and demagic the initial state a little, it's not terribly important however. At time of commit, confirmed to be working at least well enough for accelerated X (and where tested, for 3D apps) on NV40, NV43, NV44, NV46, NV49, NV4A, NV4B and NV4E. A module option has been added to force the use of external firmware blobs if it becomes required. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
134 lines
3.0 KiB
C
134 lines
3.0 KiB
C
#ifndef __NOUVEAU_GRCTX_H__
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#define __NOUVEAU_GRCTX_H__
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struct nouveau_grctx {
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struct drm_device *dev;
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enum {
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NOUVEAU_GRCTX_PROG,
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NOUVEAU_GRCTX_VALS
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} mode;
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void *data;
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uint32_t ctxprog_max;
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uint32_t ctxprog_len;
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uint32_t ctxprog_reg;
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int ctxprog_label[32];
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uint32_t ctxvals_pos;
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uint32_t ctxvals_base;
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};
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#ifdef CP_CTX
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static inline void
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cp_out(struct nouveau_grctx *ctx, uint32_t inst)
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{
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uint32_t *ctxprog = ctx->data;
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if (ctx->mode != NOUVEAU_GRCTX_PROG)
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return;
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BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
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ctxprog[ctx->ctxprog_len++] = inst;
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}
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static inline void
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cp_lsr(struct nouveau_grctx *ctx, uint32_t val)
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{
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cp_out(ctx, CP_LOAD_SR | val);
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}
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static inline void
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cp_ctx(struct nouveau_grctx *ctx, uint32_t reg, uint32_t length)
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{
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ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
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ctx->ctxvals_base = ctx->ctxvals_pos;
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ctx->ctxvals_pos = ctx->ctxvals_base + length;
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if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) {
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cp_lsr(ctx, length);
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length = 0;
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}
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cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg);
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}
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static inline void
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cp_name(struct nouveau_grctx *ctx, int name)
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{
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uint32_t *ctxprog = ctx->data;
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int i;
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if (ctx->mode != NOUVEAU_GRCTX_PROG)
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return;
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ctx->ctxprog_label[name] = ctx->ctxprog_len;
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for (i = 0; i < ctx->ctxprog_len; i++) {
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if ((ctxprog[i] & 0xfff00000) != 0xff400000)
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continue;
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if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT))
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continue;
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ctxprog[i] = (ctxprog[i] & 0x00ff00ff) |
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(ctx->ctxprog_len << CP_BRA_IP_SHIFT);
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}
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}
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static inline void
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_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
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{
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int ip = 0;
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if (mod != 2) {
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ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT;
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if (ip == 0)
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ip = 0xff000000 | (name << CP_BRA_IP_SHIFT);
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}
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cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |
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(state ? 0 : CP_BRA_IF_CLEAR));
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}
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#define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
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#ifdef CP_BRA_MOD
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#define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
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#define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
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#endif
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static inline void
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_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
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{
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cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
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}
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#define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
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static inline void
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_cp_set(struct nouveau_grctx *ctx, int flag, int state)
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{
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cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
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}
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#define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
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static inline void
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cp_pos(struct nouveau_grctx *ctx, int offset)
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{
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ctx->ctxvals_pos = offset;
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ctx->ctxvals_base = ctx->ctxvals_pos;
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cp_lsr(ctx, ctx->ctxvals_pos);
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cp_out(ctx, CP_SET_CONTEXT_POINTER);
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}
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static inline void
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gr_def(struct nouveau_grctx *ctx, uint32_t reg, uint32_t val)
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{
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if (ctx->mode != NOUVEAU_GRCTX_VALS)
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return;
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reg = (reg - 0x00400000) / 4;
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reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;
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nv_wo32(ctx->dev, ctx->data, reg, val);
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}
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#endif
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#endif
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