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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
/*
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* include/asm-v850/sim85e2.h -- Machine-dependent defs for
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* V850E2 RTL simulator
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*
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* Copyright (C) 2002,03 NEC Electronics Corporation
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* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_SIM85E2_H__
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#define __V850_SIM85E2_H__
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#include <asm/v850e2.h> /* Based on V850E2 core. */
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/* Various memory areas supported by the simulator.
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These should match the corresponding definitions in the linker script. */
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/* `instruction RAM'; instruction fetches are much faster from IRAM than
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from DRAM. */
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#define IRAM_ADDR 0
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#define IRAM_SIZE 0x00100000 /* 1MB */
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/* `data RAM', below and contiguous with the I/O space.
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Data fetches are much faster from DRAM than from IRAM. */
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#define DRAM_ADDR 0xfff00000
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#define DRAM_SIZE 0x000ff000 /* 1020KB */
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/* `external ram'. Unlike the above RAM areas, this memory is cached,
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so both instruction and data fetches should be (mostly) fast --
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however, currently only write-through caching is supported, so writes
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to ERAM will be slow. */
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#define ERAM_ADDR 0x00100000
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#define ERAM_SIZE 0x07f00000 /* 127MB (max) */
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/* Dynamic RAM; uses memory controller. */
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#define SDRAM_ADDR 0x10000000
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#define SDRAM_SIZE 0x01000000 /* 16MB */
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/* Simulator specific control registers. */
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/* NOTHAL controls whether the simulator will stop at a `halt' insn. */
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#define SIM85E2_NOTHAL_ADDR 0xffffff22
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#define SIM85E2_NOTHAL (*(volatile u8 *)SIM85E2_NOTHAL_ADDR)
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/* The simulator will stop N cycles after N is written to SIMFIN. */
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#define SIM85E2_SIMFIN_ADDR 0xffffff24
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#define SIM85E2_SIMFIN (*(volatile u16 *)SIM85E2_SIMFIN_ADDR)
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/* For <asm/irq.h> */
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#define NUM_CPU_IRQS 64
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/* For <asm/page.h> */
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#define PAGE_OFFSET SDRAM_ADDR
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/* For <asm/entry.h> */
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/* `R0 RAM', used for a few miscellaneous variables that must be accessible
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using a load instruction relative to R0. The sim85e2 simulator
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actually puts 1020K of RAM from FFF00000 to FFFFF000, so we arbitarily
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choose a small portion at the end of that. */
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#define R0_RAM_ADDR 0xFFFFE000
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/* For <asm/param.h> */
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#ifndef HZ
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#define HZ 24 /* Minimum supported frequency. */
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#endif
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#endif /* __V850_SIM85E2_H__ */
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