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84d72f9cc2
The default phase can meet most cards' requirement, but it is not the optimal one. In some extreme situation, the rx phase point produced by the following tuning process will drift quite a distance. Before tuning UHS card, this patch will set a more proper initial tx phase point, which is calculated from statistic data, and can achieve a much better tx signal quality. Signed-off-by: Wei WANG <wei_wang@realsil.com.cn> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Chris Ball <cjb@laptop.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
282 lines
7.7 KiB
C
282 lines
7.7 KiB
C
/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mfd/rtsx_pci.h>
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#include "rtsx_pcr.h"
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static u8 rts5209_get_ic_version(struct rtsx_pcr *pcr)
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{
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u8 val;
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val = rtsx_pci_readb(pcr, 0x1C);
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return val & 0x0F;
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}
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static void rts5209_fetch_vendor_settings(struct rtsx_pcr *pcr)
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{
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u32 reg;
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
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dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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if (rts5209_vendor_setting1_valid(reg)) {
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if (rts5209_reg_check_ms_pmos(reg))
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pcr->flags |= PCR_MS_PMOS;
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pcr->aspm_en = rts5209_reg_to_aspm(reg);
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}
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rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
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dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
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if (rts5209_vendor_setting2_valid(reg)) {
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pcr->sd30_drive_sel_1v8 =
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rts5209_reg_to_sd30_drive_sel_1v8(reg);
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pcr->sd30_drive_sel_3v3 =
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rts5209_reg_to_sd30_drive_sel_3v3(reg);
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pcr->card_drive_sel = rts5209_reg_to_card_drive_sel(reg);
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}
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}
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static void rts5209_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
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{
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rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
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}
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static int rts5209_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rtsx_pci_init_cmd(pcr);
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/* Turn off LED */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO, 0xFF, 0x03);
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/* Reset ASPM state to default value */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
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/* Force CLKREQ# PIN to drive 0 to request clock */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
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/* Configure GPIO as output */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_GPIO_DIR, 0xFF, 0x03);
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/* Configure driving */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
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0xFF, pcr->sd30_drive_sel_3v3);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5209_optimize_phy(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_phy_register(pcr, 0x00, 0xB966);
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}
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static int rts5209_turn_on_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
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}
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static int rts5209_turn_off_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
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}
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static int rts5209_enable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
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}
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static int rts5209_disable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
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}
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static int rts5209_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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int err;
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u8 pwr_mask, partial_pwr_on, pwr_on;
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pwr_mask = SD_POWER_MASK;
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partial_pwr_on = SD_PARTIAL_POWER_ON;
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pwr_on = SD_POWER_ON;
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if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
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pwr_mask = MS_POWER_MASK;
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partial_pwr_on = MS_PARTIAL_POWER_ON;
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pwr_on = MS_POWER_ON;
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}
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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pwr_mask, partial_pwr_on);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x04);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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/* To avoid too large in-rush current */
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udelay(150);
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x00);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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return 0;
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}
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static int rts5209_card_power_off(struct rtsx_pcr *pcr, int card)
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{
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u8 pwr_mask, pwr_off;
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pwr_mask = SD_POWER_MASK;
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pwr_off = SD_POWER_OFF;
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if ((pcr->flags & PCR_MS_PMOS) && (card == RTSX_MS_CARD)) {
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pwr_mask = MS_POWER_MASK;
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pwr_off = MS_POWER_OFF;
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}
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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pwr_mask | PMOS_STRG_MASK, pwr_off | PMOS_STRG_400mA);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x06);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5209_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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int err;
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if (voltage == OUTPUT_3V3) {
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err = rtsx_pci_write_register(pcr,
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SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
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if (err < 0)
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return err;
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} else if (voltage == OUTPUT_1V8) {
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err = rtsx_pci_write_register(pcr,
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SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
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if (err < 0)
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return err;
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static const struct pcr_ops rts5209_pcr_ops = {
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.fetch_vendor_settings = rts5209_fetch_vendor_settings,
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.extra_init_hw = rts5209_extra_init_hw,
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.optimize_phy = rts5209_optimize_phy,
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.turn_on_led = rts5209_turn_on_led,
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.turn_off_led = rts5209_turn_off_led,
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.enable_auto_blink = rts5209_enable_auto_blink,
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.disable_auto_blink = rts5209_disable_auto_blink,
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.card_power_on = rts5209_card_power_on,
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.card_power_off = rts5209_card_power_off,
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.switch_output_voltage = rts5209_switch_output_voltage,
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.cd_deglitch = NULL,
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.conv_clk_and_div_n = NULL,
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.force_power_down = rts5209_force_power_down,
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};
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/* SD Pull Control Enable:
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* SD_DAT[3:0] ==> pull up
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* SD_CD ==> pull up
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* SD_WP ==> pull up
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* SD_CMD ==> pull up
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* SD_CLK ==> pull down
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*/
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static const u32 rts5209_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
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0,
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};
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/* SD Pull Control Disable:
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* SD_DAT[3:0] ==> pull down
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* SD_CD ==> pull up
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* SD_WP ==> pull down
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* SD_CMD ==> pull down
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* SD_CLK ==> pull down
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*/
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static const u32 rts5209_sd_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
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0,
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};
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/* MS Pull Control Enable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5209_ms_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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/* MS Pull Control Disable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5209_ms_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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void rts5209_init_params(struct rtsx_pcr *pcr)
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{
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pcr->extra_caps = EXTRA_CAPS_SD_SDR50 |
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EXTRA_CAPS_SD_SDR104 | EXTRA_CAPS_MMC_8BIT;
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pcr->num_slots = 2;
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pcr->ops = &rts5209_pcr_ops;
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pcr->flags = 0;
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pcr->card_drive_sel = RTS5209_CARD_DRIVE_DEFAULT;
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pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
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pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
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pcr->aspm_en = ASPM_L1_EN;
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pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16);
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pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
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pcr->ic_version = rts5209_get_ic_version(pcr);
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pcr->sd_pull_ctl_enable_tbl = rts5209_sd_pull_ctl_enable_tbl;
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pcr->sd_pull_ctl_disable_tbl = rts5209_sd_pull_ctl_disable_tbl;
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pcr->ms_pull_ctl_enable_tbl = rts5209_ms_pull_ctl_enable_tbl;
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pcr->ms_pull_ctl_disable_tbl = rts5209_ms_pull_ctl_disable_tbl;
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}
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