Peter Zijlstra (Intel) 52f6490940 x86: Add TSX Force Abort CPUID/MSR ... Skylake systems will receive a microcode update to address a TSX errata. This microcode will (by default) clobber PMC3 when TSX instructions are (speculatively or not) executed. It also provides an MSR to cause all TSX transaction to abort and preserve PMC3. Add the CPUID enumeration and MSR definition. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>		2019-03-06 09:25:41 +01:00
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asm	x86: Add TSX Force Abort CPUID/MSR	2019-03-06 09:25:41 +01:00
uapi/asm	arch: remove redundant UAPI generic-y defines	2019-01-06 10:22:15 +09:00