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Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding <treding@nvidia.com>
17 lines
599 B
Makefile
17 lines
599 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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tegra-mc-y := mc.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
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obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
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obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
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obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
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obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
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obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o
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