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8513334115
The Kconfig currently controlling compilation of this code is: drivers/gpio/Kconfig:config GPIO_TC3589X drivers/gpio/Kconfig: bool "TC3589X GPIOs" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init was not in use by this code, the init ordering remains unchanged with this commit. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Hanumath Prasad <hanumath.prasad@stericsson.com> Cc: linux-gpio@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
355 lines
9.2 KiB
C
355 lines
9.2 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License, version 2
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* Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/gpio/driver.h>
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#include <linux/of.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/tc3589x.h>
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#include <linux/bitops.h>
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/*
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* These registers are modified under the irq bus lock and cached to avoid
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* unnecessary writes in bus_sync_unlock.
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*/
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enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
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#define CACHE_NR_REGS 4
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#define CACHE_NR_BANKS 3
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struct tc3589x_gpio {
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struct gpio_chip chip;
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struct tc3589x *tc3589x;
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struct device *dev;
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struct mutex irq_lock;
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/* Caches of interrupt control registers for bus_lock */
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u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
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u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
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};
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static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
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struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
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u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
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u8 mask = BIT(offset % 8);
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int ret;
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ret = tc3589x_reg_read(tc3589x, reg);
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if (ret < 0)
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return ret;
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return !!(ret & mask);
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}
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static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
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struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
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u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
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unsigned pos = offset % 8;
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u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
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tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
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}
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static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int val)
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{
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
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struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
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u8 reg = TC3589x_GPIODIR0 + offset / 8;
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unsigned pos = offset % 8;
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tc3589x_gpio_set(chip, offset, val);
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return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
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}
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static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
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struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
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u8 reg = TC3589x_GPIODIR0 + offset / 8;
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unsigned pos = offset % 8;
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return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
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}
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static int tc3589x_gpio_single_ended(struct gpio_chip *chip,
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unsigned offset,
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enum single_ended_mode mode)
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{
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
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struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
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/*
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* These registers are alterated at each second address
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* ODM bit 0 = drive to GND or Hi-Z (open drain)
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* ODM bit 1 = drive to VDD or Hi-Z (open source)
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*/
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u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
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u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
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unsigned pos = offset % 8;
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int ret;
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switch(mode) {
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case LINE_MODE_OPEN_DRAIN:
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/* Set open drain mode */
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ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
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if (ret)
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return ret;
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/* Enable open drain/source mode */
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return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
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case LINE_MODE_OPEN_SOURCE:
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/* Set open source mode */
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ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
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if (ret)
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return ret;
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/* Enable open drain/source mode */
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return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
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case LINE_MODE_PUSH_PULL:
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/* Disable open drain/source mode */
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return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
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default:
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break;
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}
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return -ENOTSUPP;
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}
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static struct gpio_chip template_chip = {
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.label = "tc3589x",
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.owner = THIS_MODULE,
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.direction_input = tc3589x_gpio_direction_input,
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.get = tc3589x_gpio_get,
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.direction_output = tc3589x_gpio_direction_output,
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.set = tc3589x_gpio_set,
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.set_single_ended = tc3589x_gpio_single_ended,
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.can_sleep = true,
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};
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static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
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int offset = d->hwirq;
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int regoffset = offset / 8;
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int mask = BIT(offset % 8);
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if (type == IRQ_TYPE_EDGE_BOTH) {
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tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
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return 0;
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}
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tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
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if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
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tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
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else
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tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
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if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
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tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
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else
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tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
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return 0;
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}
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static void tc3589x_gpio_irq_lock(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
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mutex_lock(&tc3589x_gpio->irq_lock);
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}
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static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
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struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
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static const u8 regmap[] = {
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[REG_IBE] = TC3589x_GPIOIBE0,
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[REG_IEV] = TC3589x_GPIOIEV0,
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[REG_IS] = TC3589x_GPIOIS0,
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[REG_IE] = TC3589x_GPIOIE0,
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};
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int i, j;
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for (i = 0; i < CACHE_NR_REGS; i++) {
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for (j = 0; j < CACHE_NR_BANKS; j++) {
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u8 old = tc3589x_gpio->oldregs[i][j];
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u8 new = tc3589x_gpio->regs[i][j];
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if (new == old)
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continue;
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tc3589x_gpio->oldregs[i][j] = new;
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tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
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}
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}
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mutex_unlock(&tc3589x_gpio->irq_lock);
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}
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static void tc3589x_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
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int offset = d->hwirq;
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int regoffset = offset / 8;
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int mask = BIT(offset % 8);
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tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
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}
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static void tc3589x_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
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int offset = d->hwirq;
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int regoffset = offset / 8;
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int mask = BIT(offset % 8);
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tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
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}
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static struct irq_chip tc3589x_gpio_irq_chip = {
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.name = "tc3589x-gpio",
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.irq_bus_lock = tc3589x_gpio_irq_lock,
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.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
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.irq_mask = tc3589x_gpio_irq_mask,
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.irq_unmask = tc3589x_gpio_irq_unmask,
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.irq_set_type = tc3589x_gpio_irq_set_type,
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};
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static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
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{
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struct tc3589x_gpio *tc3589x_gpio = dev;
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struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
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u8 status[CACHE_NR_BANKS];
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int ret;
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int i;
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ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
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ARRAY_SIZE(status), status);
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if (ret < 0)
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return IRQ_NONE;
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for (i = 0; i < ARRAY_SIZE(status); i++) {
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unsigned int stat = status[i];
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if (!stat)
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continue;
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while (stat) {
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int bit = __ffs(stat);
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int line = i * 8 + bit;
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int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
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line);
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handle_nested_irq(irq);
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stat &= ~(1 << bit);
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}
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tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
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}
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return IRQ_HANDLED;
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}
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static int tc3589x_gpio_probe(struct platform_device *pdev)
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{
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struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
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struct device_node *np = pdev->dev.of_node;
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struct tc3589x_gpio *tc3589x_gpio;
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int ret;
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int irq;
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if (!np) {
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dev_err(&pdev->dev, "No Device Tree node found\n");
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return -EINVAL;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
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GFP_KERNEL);
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if (!tc3589x_gpio)
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return -ENOMEM;
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mutex_init(&tc3589x_gpio->irq_lock);
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tc3589x_gpio->dev = &pdev->dev;
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tc3589x_gpio->tc3589x = tc3589x;
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tc3589x_gpio->chip = template_chip;
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tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
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tc3589x_gpio->chip.parent = &pdev->dev;
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tc3589x_gpio->chip.base = -1;
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tc3589x_gpio->chip.of_node = np;
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/* Bring the GPIO module out of reset */
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ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
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TC3589x_RSTCTRL_GPIRST, 0);
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if (ret < 0)
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return ret;
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ret = devm_request_threaded_irq(&pdev->dev,
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irq, NULL, tc3589x_gpio_irq,
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IRQF_ONESHOT, "tc3589x-gpio",
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tc3589x_gpio);
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if (ret) {
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dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
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return ret;
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}
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ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
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tc3589x_gpio);
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if (ret) {
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dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
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return ret;
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}
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ret = gpiochip_irqchip_add(&tc3589x_gpio->chip,
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&tc3589x_gpio_irq_chip,
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0,
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handle_simple_irq,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_err(&pdev->dev,
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"could not connect irqchip to gpiochip\n");
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return ret;
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}
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gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
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&tc3589x_gpio_irq_chip,
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irq,
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NULL);
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platform_set_drvdata(pdev, tc3589x_gpio);
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return 0;
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}
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static struct platform_driver tc3589x_gpio_driver = {
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.driver.name = "tc3589x-gpio",
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.driver.owner = THIS_MODULE,
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.probe = tc3589x_gpio_probe,
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};
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static int __init tc3589x_gpio_init(void)
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{
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return platform_driver_register(&tc3589x_gpio_driver);
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}
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subsys_initcall(tc3589x_gpio_init);
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