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1a20cb2d7d
Use devm_gpiochip_add_data() for GPIO registration. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
289 lines
8.1 KiB
C
289 lines
8.1 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/of_platform.h>
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#include <linux/mutex.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <lantiq_soc.h>
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/*
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* The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
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* peripheral controller used to drive external shift register cascades. At most
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* 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
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* to drive the 2 LSBs of the cascade automatically.
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*/
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/* control register 0 */
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#define XWAY_STP_CON0 0x00
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/* control register 1 */
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#define XWAY_STP_CON1 0x04
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/* data register 0 */
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#define XWAY_STP_CPU0 0x08
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/* data register 1 */
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#define XWAY_STP_CPU1 0x0C
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/* access register */
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#define XWAY_STP_AR 0x10
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/* software or hardware update select bit */
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#define XWAY_STP_CON_SWU BIT(31)
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/* automatic update rates */
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#define XWAY_STP_2HZ 0
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#define XWAY_STP_4HZ BIT(23)
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#define XWAY_STP_8HZ BIT(24)
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#define XWAY_STP_10HZ (BIT(24) | BIT(23))
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#define XWAY_STP_SPEED_MASK (0xf << 23)
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/* clock source for automatic update */
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#define XWAY_STP_UPD_FPI BIT(31)
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#define XWAY_STP_UPD_MASK (BIT(31) | BIT(30))
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/* let the adsl core drive the 2 LSBs */
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#define XWAY_STP_ADSL_SHIFT 24
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#define XWAY_STP_ADSL_MASK 0x3
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/* 2 groups of 3 bits can be driven by the phys */
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#define XWAY_STP_PHY_MASK 0x7
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#define XWAY_STP_PHY1_SHIFT 27
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#define XWAY_STP_PHY2_SHIFT 15
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/* STP has 3 groups of 8 bits */
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#define XWAY_STP_GROUP0 BIT(0)
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#define XWAY_STP_GROUP1 BIT(1)
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#define XWAY_STP_GROUP2 BIT(2)
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#define XWAY_STP_GROUP_MASK (0x7)
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/* Edge configuration bits */
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#define XWAY_STP_FALLING BIT(26)
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#define XWAY_STP_EDGE_MASK BIT(26)
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#define xway_stp_r32(m, reg) __raw_readl(m + reg)
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#define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
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#define xway_stp_w32_mask(m, clear, set, reg) \
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ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \
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m + reg)
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struct xway_stp {
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struct gpio_chip gc;
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void __iomem *virt;
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u32 edge; /* rising or falling edge triggered shift register */
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u32 shadow; /* shadow the shift registers state */
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u8 groups; /* we can drive 1-3 groups of 8bit each */
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u8 dsl; /* the 2 LSBs can be driven by the dsl core */
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u8 phy1; /* 3 bits can be driven by phy1 */
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u8 phy2; /* 3 bits can be driven by phy2 */
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u8 reserved; /* mask out the hw driven bits in gpio_request */
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};
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/**
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* xway_stp_set() - gpio_chip->set - set gpios.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* Set the shadow value and call ltq_ebu_apply.
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*/
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static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
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{
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struct xway_stp *chip = gpiochip_get_data(gc);
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if (val)
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chip->shadow |= BIT(gpio);
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else
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chip->shadow &= ~BIT(gpio);
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xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
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xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
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}
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/**
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* xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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* @val: Value to be written to specified signal.
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*
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* Same as xway_stp_set, always returns 0.
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*/
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static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
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{
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xway_stp_set(gc, gpio, val);
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return 0;
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}
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/**
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* xway_stp_request() - gpio_chip->request
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* @gc: Pointer to gpio_chip device structure.
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* @gpio: GPIO signal number.
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*
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* We mask out the HW driven pins
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*/
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static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
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{
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struct xway_stp *chip = gpiochip_get_data(gc);
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if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
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dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
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return -ENODEV;
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}
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return 0;
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}
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/**
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* xway_stp_hw_init() - Configure the STP unit and enable the clock gate
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* @virt: pointer to the remapped register range
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*/
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static int xway_stp_hw_init(struct xway_stp *chip)
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{
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/* sane defaults */
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xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
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xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
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xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
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xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
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xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
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/* apply edge trigger settings for the shift register */
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xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
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chip->edge, XWAY_STP_CON0);
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/* apply led group settings */
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xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
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chip->groups, XWAY_STP_CON1);
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/* tell the hardware which pins are controlled by the dsl modem */
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xway_stp_w32_mask(chip->virt,
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XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
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chip->dsl << XWAY_STP_ADSL_SHIFT,
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XWAY_STP_CON0);
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/* tell the hardware which pins are controlled by the phys */
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xway_stp_w32_mask(chip->virt,
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XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
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chip->phy1 << XWAY_STP_PHY1_SHIFT,
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XWAY_STP_CON0);
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xway_stp_w32_mask(chip->virt,
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XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
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chip->phy2 << XWAY_STP_PHY2_SHIFT,
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XWAY_STP_CON1);
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/* mask out the hw driven bits in gpio_request */
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chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;
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/*
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* if we have pins that are driven by hw, we need to tell the stp what
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* clock to use as a timer.
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*/
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if (chip->reserved)
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xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
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XWAY_STP_UPD_FPI, XWAY_STP_CON1);
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return 0;
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}
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static int xway_stp_probe(struct platform_device *pdev)
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{
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struct resource *res;
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u32 shadow, groups, dsl, phy;
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struct xway_stp *chip;
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struct clk *clk;
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int ret = 0;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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chip->virt = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(chip->virt))
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return PTR_ERR(chip->virt);
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chip->gc.parent = &pdev->dev;
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chip->gc.label = "stp-xway";
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chip->gc.direction_output = xway_stp_dir_out;
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chip->gc.set = xway_stp_set;
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chip->gc.request = xway_stp_request;
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chip->gc.base = -1;
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chip->gc.owner = THIS_MODULE;
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/* store the shadow value if one was passed by the devicetree */
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if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
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chip->shadow = shadow;
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/* find out which gpio groups should be enabled */
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if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
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chip->groups = groups & XWAY_STP_GROUP_MASK;
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else
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chip->groups = XWAY_STP_GROUP0;
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chip->gc.ngpio = fls(chip->groups) * 8;
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/* find out which gpios are controlled by the dsl core */
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if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
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chip->dsl = dsl & XWAY_STP_ADSL_MASK;
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/* find out which gpios are controlled by the phys */
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if (of_machine_is_compatible("lantiq,ar9") ||
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of_machine_is_compatible("lantiq,gr9") ||
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of_machine_is_compatible("lantiq,vr9")) {
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if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
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chip->phy1 = phy & XWAY_STP_PHY_MASK;
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if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
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chip->phy2 = phy & XWAY_STP_PHY_MASK;
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}
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/* check which edge trigger we should use, default to a falling edge */
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if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
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chip->edge = XWAY_STP_FALLING;
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clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "Failed to get clock\n");
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return PTR_ERR(clk);
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}
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clk_enable(clk);
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ret = xway_stp_hw_init(chip);
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if (!ret)
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ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
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if (!ret)
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dev_info(&pdev->dev, "Init done\n");
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return ret;
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}
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static const struct of_device_id xway_stp_match[] = {
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{ .compatible = "lantiq,gpio-stp-xway" },
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{},
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};
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MODULE_DEVICE_TABLE(of, xway_stp_match);
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static struct platform_driver xway_stp_driver = {
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.probe = xway_stp_probe,
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.driver = {
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.name = "gpio-stp-xway",
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.of_match_table = xway_stp_match,
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},
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};
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static int __init xway_stp_init(void)
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{
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return platform_driver_register(&xway_stp_driver);
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}
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subsys_initcall(xway_stp_init);
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