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Add MT8188 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-11-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs mfgcfg_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_MFG(_id, _name, _parent, _shift) \
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GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
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static const struct mtk_gate mfgcfg_clks[] = {
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GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "mfg_ck_fast_ref", 0),
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};
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static const struct mtk_clk_desc mfgcfg_desc = {
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.clks = mfgcfg_clks,
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.num_clks = ARRAY_SIZE(mfgcfg_clks),
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};
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static const struct of_device_id of_match_clk_mt8188_mfgcfg[] = {
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{ .compatible = "mediatek,mt8188-mfgcfg", .data = &mfgcfg_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_mfgcfg);
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static struct platform_driver clk_mt8188_mfgcfg_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8188-mfgcfg",
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.of_match_table = of_match_clk_mt8188_mfgcfg,
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},
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};
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module_platform_driver(clk_mt8188_mfgcfg_drv);
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MODULE_LICENSE("GPL");
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