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65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
157 lines
4.4 KiB
C
157 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-cpumux.h"
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "reset.h"
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#define GATE_ICG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
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_shift, &mtk_clk_gate_ops_setclr)
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static struct clk_hw_onecell_data *infra_clk_data;
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static const struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = 0x0040,
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.clr_ofs = 0x0044,
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.sta_ofs = 0x0048,
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};
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static const char * const ca53_parents[] __initconst = {
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"clk26m",
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"armca7pll",
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"mainpll",
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"univpll"
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};
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static const char * const ca72_parents[] __initconst = {
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"clk26m",
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"armca15pll",
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"mainpll",
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"univpll"
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};
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static const struct mtk_composite cpu_muxes[] = {
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MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
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MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2),
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};
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static const struct mtk_fixed_factor infra_early_divs[] = {
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FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
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};
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static const struct mtk_gate infra_gates[] = {
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GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
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GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
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GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
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GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
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GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
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GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
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GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
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GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
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GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
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GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
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GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
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};
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static u16 infrasys_rst_ofs[] = { 0x30, 0x34 };
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = infrasys_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
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};
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static const struct of_device_id of_match_clk_mt8173_infracfg[] = {
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{ .compatible = "mediatek,mt8173-infracfg" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_infracfg);
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static void clk_mt8173_infra_init_early(struct device_node *node)
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{
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int i;
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infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
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if (!infra_clk_data)
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return;
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for (i = 0; i < CLK_INFRA_NR_CLK; i++)
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infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
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mtk_clk_register_factors(infra_early_divs,
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ARRAY_SIZE(infra_early_divs), infra_clk_data);
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of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);
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}
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CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
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clk_mt8173_infra_init_early);
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static int clk_mt8173_infracfg_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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int r;
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r = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
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ARRAY_SIZE(infra_gates), infra_clk_data);
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if (r)
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return r;
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r = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
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ARRAY_SIZE(cpu_muxes), infra_clk_data);
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if (r)
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goto unregister_gates;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data);
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if (r)
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goto unregister_cpumuxes;
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r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
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if (r)
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goto unregister_clk_hw;
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return 0;
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unregister_clk_hw:
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of_clk_del_provider(node);
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unregister_cpumuxes:
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data);
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unregister_gates:
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mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data);
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return r;
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}
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static int clk_mt8173_infracfg_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
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mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt8173_infracfg_drv = {
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.driver = {
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.name = "clk-mt8173-infracfg",
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.of_match_table = of_match_clk_mt8173_infracfg,
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},
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.probe = clk_mt8173_infracfg_probe,
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.remove = clk_mt8173_infracfg_remove,
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};
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module_platform_driver(clk_mt8173_infracfg_drv);
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MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver");
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MODULE_LICENSE("GPL");
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