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cb9eee590a
smatch reports
drivers/clk/mediatek/clk-fhctl.c:17:27: warning: symbol
'fhctl_offset_v1' was not declared. Should it be static?
drivers/clk/mediatek/clk-fhctl.c:30:27: warning: symbol
'fhctl_offset_v2' was not declared. Should it be static?
These variables are only used in one file so should be static.
Signed-off-by: Tom Rix <trix@redhat.com>
Link: https://lore.kernel.org/r/20230406010935.1944976-1-trix@redhat.com
Fixes: 8da312d657
("clk: mediatek: fhctl: Add support for older fhctl register layout")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
265 lines
6.8 KiB
C
265 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
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*/
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include "clk-mtk.h"
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#include "clk-pllfh.h"
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#include "clk-fhctl.h"
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#define PERCENT_TO_DDSLMT(dds, percent_m10) \
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((((dds) * (percent_m10)) >> 5) / 100)
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static const struct fhctl_offset fhctl_offset_v1 = {
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.offset_hp_en = 0x0,
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.offset_clk_con = 0x4,
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.offset_rst_con = 0x8,
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.offset_slope0 = 0xc,
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.offset_slope1 = 0x10,
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.offset_cfg = 0x0,
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.offset_updnlmt = 0x4,
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.offset_dds = 0x8,
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.offset_dvfs = 0xc,
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.offset_mon = 0x10,
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};
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static const struct fhctl_offset fhctl_offset_v2 = {
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.offset_hp_en = 0x0,
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.offset_clk_con = 0x8,
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.offset_rst_con = 0xc,
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.offset_slope0 = 0x10,
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.offset_slope1 = 0x14,
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.offset_cfg = 0x0,
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.offset_updnlmt = 0x4,
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.offset_dds = 0x8,
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.offset_dvfs = 0xc,
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.offset_mon = 0x10,
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};
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const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v)
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{
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switch (v) {
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case FHCTL_PLLFH_V1:
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return &fhctl_offset_v1;
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case FHCTL_PLLFH_V2:
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return &fhctl_offset_v2;
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default:
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return ERR_PTR(-EINVAL);
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};
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}
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static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
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const struct fh_pll_data *data)
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{
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pr_info("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",
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readl(regs->reg_hp_en), readl(regs->reg_clk_con),
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readl(regs->reg_slope0), readl(regs->reg_slope1));
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pr_info("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",
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readl(regs->reg_cfg), readl(regs->reg_updnlmt),
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readl(regs->reg_dds), readl(regs->reg_dvfs),
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readl(regs->reg_mon));
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pr_info("pcw<%x>\n", readl(pll->pcw_addr));
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}
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static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
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const struct fh_pll_data *data, u32 rate)
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{
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u32 updnlmt_val, r;
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writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
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writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
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writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
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if (rate > 0) {
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/* Set the relative parameter registers (dt/df/upbnd/downbnd) */
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r = readl(regs->reg_cfg);
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r &= ~(data->msk_frddsx_dys);
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r |= (data->df_val << (ffs(data->msk_frddsx_dys) - 1));
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writel(r, regs->reg_cfg);
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r = readl(regs->reg_cfg);
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r &= ~(data->msk_frddsx_dts);
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r |= (data->dt_val << (ffs(data->msk_frddsx_dts) - 1));
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writel(r, regs->reg_cfg);
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writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
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regs->reg_dds);
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/* Calculate UPDNLMT */
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updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &
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data->dds_mask), rate) <<
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data->updnlmt_shft;
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writel(updnlmt_val, regs->reg_updnlmt);
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writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
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regs->reg_hp_en);
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/* Enable SSC */
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writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
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/* Enable Hopping control */
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writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
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} else {
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/* Switch to APMIXEDSYS control */
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writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
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regs->reg_hp_en);
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/* Wait for DDS to be stable */
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udelay(30);
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}
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return 0;
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}
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static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
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const struct fh_pll_data *data,
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struct fh_pll_state *state, unsigned int new_dds)
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{
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u32 dds_mask = data->dds_mask;
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u32 mon_dds = 0;
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u32 con_pcw_tmp;
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int ret;
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if (state->ssc_rate)
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fhctl_set_ssc_regs(pll, regs, data, 0);
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writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
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regs->reg_dds);
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writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
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writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
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writel(data->slope0_value, regs->reg_slope0);
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writel(data->slope1_value, regs->reg_slope1);
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writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
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writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);
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/* Wait 1000 us until DDS stable */
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ret = readl_poll_timeout_atomic(regs->reg_mon, mon_dds,
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(mon_dds & dds_mask) == new_dds,
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10, 1000);
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if (ret) {
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pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);
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dump_hw(pll, regs, data);
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}
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con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
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con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |
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data->pcwchg);
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writel(con_pcw_tmp, pll->pcw_addr);
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writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
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if (state->ssc_rate)
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fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);
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return ret;
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}
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static unsigned int __get_postdiv(struct mtk_clk_pll *pll)
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{
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unsigned int regval;
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regval = readl(pll->pd_addr) >> pll->data->pd_shift;
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regval &= POSTDIV_MASK;
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return BIT(regval);
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}
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static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)
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{
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unsigned int regval;
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regval = readl(pll->pd_addr);
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regval &= ~(POSTDIV_MASK << pll->data->pd_shift);
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regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
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writel(regval, pll->pd_addr);
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}
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static int fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds,
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unsigned int postdiv)
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{
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const struct fh_pll_data *data = &fh->pllfh_data->data;
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struct fh_pll_state *state = &fh->pllfh_data->state;
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struct fh_pll_regs *regs = &fh->regs;
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struct mtk_clk_pll *pll = &fh->clk_pll;
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spinlock_t *lock = fh->lock;
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unsigned int pll_postdiv;
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unsigned long flags = 0;
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int ret;
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if (postdiv) {
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pll_postdiv = __get_postdiv(pll);
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if (postdiv > pll_postdiv)
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__set_postdiv(pll, postdiv);
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}
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spin_lock_irqsave(lock, flags);
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ret = hopping_hw_flow(pll, regs, data, state, new_dds);
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spin_unlock_irqrestore(lock, flags);
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if (postdiv && postdiv < pll_postdiv)
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__set_postdiv(pll, postdiv);
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return ret;
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}
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static int fhctl_ssc_enable(struct mtk_fh *fh, u32 rate)
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{
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const struct fh_pll_data *data = &fh->pllfh_data->data;
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struct fh_pll_state *state = &fh->pllfh_data->state;
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struct fh_pll_regs *regs = &fh->regs;
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struct mtk_clk_pll *pll = &fh->clk_pll;
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spinlock_t *lock = fh->lock;
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unsigned long flags = 0;
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spin_lock_irqsave(lock, flags);
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fhctl_set_ssc_regs(pll, regs, data, rate);
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state->ssc_rate = rate;
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spin_unlock_irqrestore(lock, flags);
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return 0;
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}
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static const struct fh_operation fhctl_ops = {
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.hopping = fhctl_hopping,
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.ssc_enable = fhctl_ssc_enable,
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};
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const struct fh_operation *fhctl_get_ops(void)
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{
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return &fhctl_ops;
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}
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void fhctl_hw_init(struct mtk_fh *fh)
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{
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const struct fh_pll_data data = fh->pllfh_data->data;
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struct fh_pll_state state = fh->pllfh_data->state;
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struct fh_pll_regs regs = fh->regs;
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u32 val;
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/* initial hw register */
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val = readl(regs.reg_clk_con) | BIT(data.fh_id);
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writel(val, regs.reg_clk_con);
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val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);
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writel(val, regs.reg_rst_con);
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val = readl(regs.reg_rst_con) | BIT(data.fh_id);
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writel(val, regs.reg_rst_con);
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writel(0x0, regs.reg_cfg);
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writel(0x0, regs.reg_updnlmt);
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writel(0x0, regs.reg_dds);
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/* enable ssc if needed */
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if (state.ssc_rate)
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fh->ops->ssc_enable(fh, state.ssc_rate);
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}
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