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We return 1 if the IOMMU has been detected. Zero or an error number if we failed to find it. This is in preperation of using the IOMMU_INIT so that we can detect whether an IOMMU is present. I have not tested this for regression on Calgary, nor on AMD Vi chipsets as I don't have that hardware. CC: Muli Ben-Yehuda <muli@il.ibm.com> CC: "Jon D. Mason" <jdmason@kudzu.us> CC: "Darrick J. Wong" <djwong@us.ibm.com> CC: Jesse Barnes <jbarnes@virtuousgeek.org> CC: David Woodhouse <David.Woodhouse@intel.com> CC: Chris Wright <chrisw@sous-sol.org> CC: Yinghai Lu <yinghai@kernel.org> CC: Joerg Roedel <joerg.roedel@amd.com> CC: H. Peter Anvin <hpa@zytor.com> CC: Fujita Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> LKML-Reference: <1282845485-8991-3-git-send-email-konrad.wilk@oracle.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/*
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* Derived from include/asm-powerpc/iommu.h
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*
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* Copyright IBM Corporation, 2006-2007
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*
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* Author: Jon Mason <jdmason@us.ibm.com>
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* Author: Muli Ben-Yehuda <muli@il.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_X86_CALGARY_H
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#define _ASM_X86_CALGARY_H
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/timer.h>
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#include <asm/types.h>
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struct iommu_table {
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struct cal_chipset_ops *chip_ops; /* chipset specific funcs */
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unsigned long it_base; /* mapped address of tce table */
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unsigned long it_hint; /* Hint for next alloc */
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unsigned long *it_map; /* A simple allocation bitmap for now */
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void __iomem *bbar; /* Bridge BAR */
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u64 tar_val; /* Table Address Register */
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struct timer_list watchdog_timer;
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spinlock_t it_lock; /* Protects it_map */
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unsigned int it_size; /* Size of iommu table in entries */
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unsigned char it_busno; /* Bus number this table belongs to */
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};
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struct cal_chipset_ops {
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void (*handle_quirks)(struct iommu_table *tbl, struct pci_dev *dev);
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void (*tce_cache_blast)(struct iommu_table *tbl);
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void (*dump_error_regs)(struct iommu_table *tbl);
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};
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#define TCE_TABLE_SIZE_UNSPECIFIED ~0
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#define TCE_TABLE_SIZE_64K 0
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#define TCE_TABLE_SIZE_128K 1
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#define TCE_TABLE_SIZE_256K 2
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#define TCE_TABLE_SIZE_512K 3
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#define TCE_TABLE_SIZE_1M 4
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#define TCE_TABLE_SIZE_2M 5
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#define TCE_TABLE_SIZE_4M 6
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#define TCE_TABLE_SIZE_8M 7
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extern int use_calgary;
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#ifdef CONFIG_CALGARY_IOMMU
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extern int detect_calgary(void);
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#else
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static inline int detect_calgary(void) { return -ENODEV; }
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#endif
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#endif /* _ASM_X86_CALGARY_H */
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