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61aaaa8110
There's no reason to have "status" properties in examples. "okay" is the
default, and "disabled" turns off some schema checks ('required'
specifically).
Enabling qca,ar71xx causes a warning, so let's fix the node names:
Documentation/devicetree/bindings/net/qca,ar71xx.example.dt.yaml: phy@3: '#phy-cells' is a required property
From schema: schemas/phy/phy-provider.yaml
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Robert Marko <robert.marko@sartura.hr>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Ramesh Shanmugasundaram <rashanmu@gmail.com>
Cc: "G. Jaya Kumaran" <vineetha.g.jaya.kumaran@intel.com>
Cc: ChiYuan Huang <cy_huang@richtek.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Dilip Kota <eswara.kota@linux.intel.com>
Cc: Karol Gugala <kgugala@antmicro.com>
Cc: Mateusz Holenko <mholenko@antmicro.com>
Cc: Olivier Moysan <olivier.moysan@st.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-media@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-rtc@vger.kernel.org
Cc: alsa-devel@alsa-project.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Rui Miguel Silva <rmfrfs@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> # For media
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210720172025.363238-1-robh@kernel.org
270 lines
9.1 KiB
YAML
270 lines
9.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/renesas,drif.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
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maintainers:
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- Ramesh Shanmugasundaram <rashanmu@gmail.com>
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- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
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description: |
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R-Car Gen3 DRIF is a SPI like receive only slave device. A general
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representation of DRIF interfacing with a master device is shown below.
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+---------------------+ +---------------------+
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| |-----SCK------->|CLK |
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| Master |-----SS-------->|SYNC DRIFn (slave) |
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| |-----SD0------->|D0 |
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| |-----SD1------->|D1 |
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+---------------------+ +---------------------+
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As per datasheet, each DRIF channel (drifn) is made up of two internal
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channels (drifn0 & drifn1). These two internal channels share the common
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CLK & SYNC. Each internal channel has its own dedicated resources like
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irq, dma channels, address space & clock. This internal split is not
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visible to the external master device.
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The device tree model represents each internal channel as a separate node.
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The internal channels sharing the CLK & SYNC are tied together by their
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phandles using a property called "renesas,bonding". For the rest of
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the documentation, unless explicitly stated, the word channel implies an
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internal channel.
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When both internal channels are enabled they need to be managed together
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as one (i.e.) they cannot operate alone as independent devices. Out of the
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two, one of them needs to act as a primary device that accepts common
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properties of both the internal channels. This channel is identified by a
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property called "renesas,primary-bond".
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To summarize,
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* When both the internal channels that are bonded together are enabled,
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the zeroth channel is selected as primary-bond. This channels accepts
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properties common to all the members of the bond.
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* When only one of the bonded channels need to be enabled, the property
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"renesas,bonding" or "renesas,primary-bond" will have no effect. That
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enabled channel can act alone as any other independent device.
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properties:
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compatible:
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items:
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- enum:
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- renesas,r8a7795-drif # R-Car H3
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- renesas,r8a7796-drif # R-Car M3-W
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- renesas,r8a77965-drif # R-Car M3-N
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- renesas,r8a77990-drif # R-Car E3
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- const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: fck
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resets:
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maxItems: 1
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dmas:
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minItems: 1
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maxItems: 2
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dma-names:
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minItems: 1
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items:
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- const: rx
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- const: rx
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renesas,bonding:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The phandle to the other internal channel of DRIF
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power-domains:
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maxItems: 1
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renesas,primary-bond:
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type: boolean
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description:
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Indicates that the channel acts as primary among the bonded channels.
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port:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Child port node corresponding to the data input. The port node must
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contain at least one endpoint.
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properties:
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endpoint:
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$ref: /schemas/graph.yaml#/$defs/endpoint-base
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unevaluatedProperties: false
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properties:
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sync-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1]
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description:
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Indicates sync signal polarity, 0/1 for low/high respectively.
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This property maps to SYNCAC bit in the hardware manual. The
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default is 1 (active high).
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- dmas
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- dma-names
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- renesas,bonding
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- power-domains
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allOf:
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- if:
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required:
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- renesas,primary-bond
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then:
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required:
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- pinctrl-0
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- pinctrl-names
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- port
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- if:
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required:
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- port
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then:
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required:
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- pinctrl-0
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- pinctrl-names
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else:
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properties:
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pinctrl-0: false
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pinctrl-names: false
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additionalProperties: false
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examples:
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# Example with both internal channels enabled.
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#
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# When interfacing with a third party tuner device with two data pins as shown
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# below.
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#
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# +---------------------+ +---------------------+
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# | |-----SCK------->|CLK |
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# | Master |-----SS-------->|SYNC DRIFn (slave) |
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# | |-----SD0------->|D0 |
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# | |-----SD1------->|D1 |
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# +---------------------+ +---------------------+
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- |
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7795-sysc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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drif00: rif@e6f40000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f40000 0 0x64>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 515>;
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clock-names = "fck";
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dmas = <&dmac1 0x20>, <&dmac2 0x20>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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renesas,bonding = <&drif01>;
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resets = <&cpg 515>;
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renesas,primary-bond;
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pinctrl-0 = <&drif0_pins>;
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pinctrl-names = "default";
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port {
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drif0_ep: endpoint {
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remote-endpoint = <&tuner_ep>;
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};
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};
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};
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drif01: rif@e6f50000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f50000 0 0x64>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 514>;
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clock-names = "fck";
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dmas = <&dmac1 0x22>, <&dmac2 0x22>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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renesas,bonding = <&drif00>;
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resets = <&cpg 514>;
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};
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};
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# Example with internal channel 1 alone enabled.
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#
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# When interfacing with a third party tuner device with one data pin as shown
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# below.
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#
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# +---------------------+ +---------------------+
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# | |-----SCK------->|CLK |
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# | Master |-----SS-------->|SYNC DRIFn (slave) |
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# | | |D0 (unused) |
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# | |-----SD-------->|D1 |
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# +---------------------+ +---------------------+
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- |
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#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7795-sysc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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drif10: rif@e6f60000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f60000 0 0x64>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 513>;
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clock-names = "fck";
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dmas = <&dmac1 0x24>, <&dmac2 0x24>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 513>;
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renesas,bonding = <&drif11>;
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};
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drif11: rif@e6f70000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f70000 0 0x64>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 512>;
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clock-names = "fck";
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dmas = <&dmac1 0x26>, <&dmac2 0x26>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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resets = <&cpg 512>;
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renesas,bonding = <&drif10>;
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pinctrl-0 = <&drif1_pins>;
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pinctrl-names = "default";
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port {
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drif1_ep: endpoint {
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remote-endpoint = <&tuner_ep1>;
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sync-active = <0>;
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};
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};
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};
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};
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...
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