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This patch adds DT binding document for zynqmp modepin GPIO controller. Modepin GPIO controller has four GPIO pins which can be configurable as input or output. Modepin driver is a bridge between the peripheral driver and GPIO pins. It has set and get APIs for accessing GPIO pins, based on the device-tree entry of reset-gpio property in the peripheral driver, every pin can be configured as input/output and trigger GPIO pin. For more information please refer zynqMp TRM link: Link: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Chapter 2: Signals, Interfaces, and Pins Table 2-2: Clock, Reset, and Configuration Pins - PS_MODE Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
44 lines
918 B
YAML
44 lines
918 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: ZynqMP Mode Pin GPIO controller
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description:
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PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
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GPIO controller with configurable from numbers of pins (from 0 to 3 per
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PS_MODE). Every pin can be configured as input/output.
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maintainers:
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- Piyush Mehta <piyush.mehta@xilinx.com>
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properties:
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compatible:
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const: xlnx,zynqmp-gpio-modepin
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gpio-controller: true
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"#gpio-cells":
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const: 2
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required:
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- compatible
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- gpio-controller
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- "#gpio-cells"
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additionalProperties: false
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examples:
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- |
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zynqmp-firmware {
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gpio {
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compatible = "xlnx,zynqmp-gpio-modepin";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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...
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