Lucas Stach 4f2ebe0059 PCI: designware: Parse bus-range property from devicetree ... This allows to explicitly specify the covered bus numbers in the devicetree, which will come in handy once we see a SoC with more than one PCIe host controller instance. Previously the driver relied on the behavior of pci_scan_root_bus() to fill in a range of 0x00-0xff if no valid range was found. We fall back to the same range if no valid DT entry was found to keep backwards compatibility, but now do it explicitly. [bhelgaas: use %pR in error message to avoid duplication] Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Mohit Kumar <mohit.kumar@st.com>		2014-09-04 14:58:48 -06:00
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bindings	PCI: designware: Parse bus-range property from devicetree	2014-09-04 14:58:48 -06:00
00-INDEX	Documentation/: update 00-INDEX files	2014-02-10 16:01:40 -08:00
booting-without-of.txt	dt/bindings: Remove all references to device_type "ethernet-phy"	2014-01-16 11:11:51 +00:00
changesets.txt	of: Transactional DT support.	2014-07-23 17:29:15 -06:00
todo.txt	of: Add todo tasklist for Devicetree	2014-07-23 17:33:01 -06:00
usage-model.txt