Like Xu 4f1fa2a1bb KVM: x86/pmu: Limit the maximum number of supported Intel GP counters ... The Intel Architectural IA32_PMCx MSRs addresses range allows for a maximum of 8 GP counters, and KVM cannot address any more. Introduce a local macro (named KVM_INTEL_PMC_MAX_GENERIC) and use it consistently to refer to the number of counters supported by KVM, thus avoiding possible out-of-bound accesses. Suggested-by: Jim Mattson <jmattson@google.com> Signed-off-by: Like Xu <likexu@tencent.com> Reviewed-by: Jim Mattson <jmattson@google.com> Message-Id: <20220919091008.60695-2-likexu@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2022-11-09 12:26:53 -05:00
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asm	KVM: x86/pmu: Limit the maximum number of supported Intel GP counters	2022-11-09 12:26:53 -05:00
uapi/asm	- SGX2 ISA support which makes enclave memory management much more	2022-08-05 10:47:40 -07:00