mirror of
https://github.com/torvalds/linux.git
synced 2024-12-23 11:21:33 +00:00
02985b9463
The SRC has auto-deasserting reset bits that control reset lines to the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset controller that can be controlled by those devices using the reset controller API. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
50 lines
1.3 KiB
Plaintext
50 lines
1.3 KiB
Plaintext
Freescale i.MX System Reset Controller
|
|
======================================
|
|
|
|
Please also refer to reset.txt in this directory for common reset
|
|
controller binding usage.
|
|
|
|
Required properties:
|
|
- compatible: Should be "fsl,<chip>-src"
|
|
- reg: should be register base and length as documented in the
|
|
datasheet
|
|
- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
|
|
in this order.
|
|
- #reset-cells: 1, see below
|
|
|
|
example:
|
|
|
|
src: src@020d8000 {
|
|
compatible = "fsl,imx6q-src";
|
|
reg = <0x020d8000 0x4000>;
|
|
interrupts = <0 91 0x04 0 96 0x04>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
Specifying reset lines connected to IP modules
|
|
==============================================
|
|
|
|
The system reset controller can be used to reset the GPU, VPU,
|
|
IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
|
|
nodes should specify the reset line on the SRC in their resets
|
|
property, containing a phandle to the SRC device node and a
|
|
RESET_INDEX specifying which module to reset, as described in
|
|
reset.txt
|
|
|
|
example:
|
|
|
|
ipu1: ipu@02400000 {
|
|
resets = <&src 2>;
|
|
};
|
|
ipu2: ipu@02800000 {
|
|
resets = <&src 4>;
|
|
};
|
|
|
|
The following RESET_INDEX values are valid for i.MX5:
|
|
GPU_RESET 0
|
|
VPU_RESET 1
|
|
IPU1_RESET 2
|
|
OPEN_VG_RESET 3
|
|
The following additional RESET_INDEX value is valid for i.MX6:
|
|
IPU2_RESET 4
|