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4f04d8f005
The virtual memory layout is described in Documentation/arm64/memory.txt. This patch adds the MMU definitions for the 4KB and 64KB translation table configurations. The SECTION_SIZE is 2MB with 4KB page and 512MB with 64KB page configuration. PHYS_OFFSET is calculated at run-time and stored in a variable (no run-time code patching at this stage). On the current implementation, both user and kernel address spaces are 512G (39-bit) each with a maximum of 256G for the RAM linear mapping. Linux uses 3 levels of translation tables with the 4K page configuration and 2 levels with the 64K configuration. Extending the memory space beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an additional level of translation tables. The SPARSEMEM configuration is global to all AArch64 platforms and allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PGTABLE_HWDEF_H
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#define __ASM_PGTABLE_HWDEF_H
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#ifdef CONFIG_ARM64_64K_PAGES
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#include <asm/pgtable-2level-hwdef.h>
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#else
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#include <asm/pgtable-3level-hwdef.h>
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#endif
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/*
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* Hardware page table definitions.
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*
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* Level 2 descriptor (PMD).
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*/
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#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
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#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
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#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
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/*
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* Section
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*/
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#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
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#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
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#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
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#define PMD_SECT_XN (_AT(pmdval_t, 1) << 54)
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
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#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
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/*
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* Level 3 descriptor (PTE).
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*/
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#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
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#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
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#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
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#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
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#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
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#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
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#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
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#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
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#define PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
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/*
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* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
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*/
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#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
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#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
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/*
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* 40-bit physical address supported.
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*/
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#define PHYS_MASK_SHIFT (40)
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#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
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/*
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* TCR flags.
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*/
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#define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0))
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#define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24))
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#define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24))
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#define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24))
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#define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24))
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#define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24))
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#define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26))
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#define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26))
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#define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26))
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#define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26))
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#define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26))
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#define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28))
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#define TCR_TG0_64K (UL(1) << 14)
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#define TCR_TG1_64K (UL(1) << 30)
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#define TCR_IPS_40BIT (UL(2) << 32)
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#define TCR_ASID16 (UL(1) << 36)
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#endif
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