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885ce72a09
The fuse programming from non-secure world is blocked, so we could only use Arm Trusted Firmware SIP call to let ATF program fuse. Because there is ECC region that could only be programmed once, so add a heler in_ecc to check the ecc region. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20191029114240.14905-5-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
277 lines
5.5 KiB
C
277 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* i.MX8 OCOTP fusebox driver
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*
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* Copyright 2019 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <linux/arm-smccc.h>
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#include <linux/firmware/imx/sci.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define IMX_SIP_OTP 0xC200000A
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#define IMX_SIP_OTP_WRITE 0x2
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enum ocotp_devtype {
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IMX8QXP,
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IMX8QM,
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};
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#define ECC_REGION BIT(0)
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#define HOLE_REGION BIT(1)
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struct ocotp_region {
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u32 start;
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u32 end;
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u32 flag;
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};
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struct ocotp_devtype_data {
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int devtype;
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int nregs;
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u32 num_region;
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struct ocotp_region region[];
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};
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struct ocotp_priv {
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struct device *dev;
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const struct ocotp_devtype_data *data;
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struct imx_sc_ipc *nvmem_ipc;
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};
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struct imx_sc_msg_misc_fuse_read {
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struct imx_sc_rpc_msg hdr;
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u32 word;
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} __packed;
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static DEFINE_MUTEX(scu_ocotp_mutex);
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static struct ocotp_devtype_data imx8qxp_data = {
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.devtype = IMX8QXP,
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.nregs = 800,
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.num_region = 3,
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.region = {
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{0x10, 0x10f, ECC_REGION},
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{0x110, 0x21F, HOLE_REGION},
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{0x220, 0x31F, ECC_REGION},
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},
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};
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static struct ocotp_devtype_data imx8qm_data = {
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.devtype = IMX8QM,
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.nregs = 800,
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.num_region = 2,
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.region = {
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{0x10, 0x10f, ECC_REGION},
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{0x1a0, 0x1ff, ECC_REGION},
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},
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};
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static bool in_hole(void *context, u32 index)
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{
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struct ocotp_priv *priv = context;
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const struct ocotp_devtype_data *data = priv->data;
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int i;
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for (i = 0; i < data->num_region; i++) {
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if (data->region[i].flag & HOLE_REGION) {
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if ((index >= data->region[i].start) &&
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(index <= data->region[i].end))
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return true;
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}
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}
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return false;
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}
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static bool in_ecc(void *context, u32 index)
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{
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struct ocotp_priv *priv = context;
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const struct ocotp_devtype_data *data = priv->data;
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int i;
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for (i = 0; i < data->num_region; i++) {
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if (data->region[i].flag & ECC_REGION) {
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if ((index >= data->region[i].start) &&
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(index <= data->region[i].end))
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return true;
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}
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}
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return false;
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}
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static int imx_sc_misc_otp_fuse_read(struct imx_sc_ipc *ipc, u32 word,
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u32 *val)
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{
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struct imx_sc_msg_misc_fuse_read msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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int ret;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_MISC;
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hdr->func = IMX_SC_MISC_FUNC_OTP_FUSE_READ;
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hdr->size = 2;
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msg.word = word;
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ret = imx_scu_call_rpc(ipc, &msg, true);
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if (ret)
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return ret;
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*val = msg.word;
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return 0;
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}
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static int imx_scu_ocotp_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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{
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struct ocotp_priv *priv = context;
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u32 count, index, num_bytes;
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u32 *buf;
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void *p;
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int i, ret;
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index = offset >> 2;
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num_bytes = round_up((offset % 4) + bytes, 4);
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count = num_bytes >> 2;
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if (count > (priv->data->nregs - index))
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count = priv->data->nregs - index;
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p = kzalloc(num_bytes, GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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mutex_lock(&scu_ocotp_mutex);
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buf = p;
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for (i = index; i < (index + count); i++) {
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if (in_hole(context, i)) {
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*buf++ = 0;
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continue;
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}
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ret = imx_sc_misc_otp_fuse_read(priv->nvmem_ipc, i, buf);
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if (ret) {
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mutex_unlock(&scu_ocotp_mutex);
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kfree(p);
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return ret;
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}
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buf++;
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}
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memcpy(val, (u8 *)p + offset % 4, bytes);
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mutex_unlock(&scu_ocotp_mutex);
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kfree(p);
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return 0;
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}
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static int imx_scu_ocotp_write(void *context, unsigned int offset,
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void *val, size_t bytes)
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{
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struct ocotp_priv *priv = context;
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struct arm_smccc_res res;
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u32 *buf = val;
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u32 tmp;
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u32 index;
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int ret;
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/* allow only writing one complete OTP word at a time */
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if ((bytes != 4) || (offset % 4))
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return -EINVAL;
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index = offset >> 2;
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if (in_hole(context, index))
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return -EINVAL;
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if (in_ecc(context, index)) {
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pr_warn("ECC region, only program once\n");
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mutex_lock(&scu_ocotp_mutex);
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ret = imx_sc_misc_otp_fuse_read(priv->nvmem_ipc, index, &tmp);
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mutex_unlock(&scu_ocotp_mutex);
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if (ret)
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return ret;
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if (tmp) {
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pr_warn("ECC region, already has value: %x\n", tmp);
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return -EIO;
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}
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}
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mutex_lock(&scu_ocotp_mutex);
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arm_smccc_smc(IMX_SIP_OTP, IMX_SIP_OTP_WRITE, index, *buf,
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0, 0, 0, 0, &res);
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mutex_unlock(&scu_ocotp_mutex);
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return res.a0;
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}
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static struct nvmem_config imx_scu_ocotp_nvmem_config = {
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.name = "imx-scu-ocotp",
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.read_only = false,
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.word_size = 4,
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.stride = 1,
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.owner = THIS_MODULE,
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.reg_read = imx_scu_ocotp_read,
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.reg_write = imx_scu_ocotp_write,
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};
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static const struct of_device_id imx_scu_ocotp_dt_ids[] = {
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{ .compatible = "fsl,imx8qxp-scu-ocotp", (void *)&imx8qxp_data },
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{ .compatible = "fsl,imx8qm-scu-ocotp", (void *)&imx8qm_data },
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{ },
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};
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MODULE_DEVICE_TABLE(of, imx_scu_ocotp_dt_ids);
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static int imx_scu_ocotp_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ocotp_priv *priv;
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struct nvmem_device *nvmem;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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ret = imx_scu_get_handle(&priv->nvmem_ipc);
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if (ret)
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return ret;
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priv->data = of_device_get_match_data(dev);
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priv->dev = dev;
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imx_scu_ocotp_nvmem_config.size = 4 * priv->data->nregs;
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imx_scu_ocotp_nvmem_config.dev = dev;
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imx_scu_ocotp_nvmem_config.priv = priv;
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nvmem = devm_nvmem_register(dev, &imx_scu_ocotp_nvmem_config);
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return PTR_ERR_OR_ZERO(nvmem);
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}
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static struct platform_driver imx_scu_ocotp_driver = {
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.probe = imx_scu_ocotp_probe,
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.driver = {
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.name = "imx_scu_ocotp",
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.of_match_table = imx_scu_ocotp_dt_ids,
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},
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};
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module_platform_driver(imx_scu_ocotp_driver);
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MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
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MODULE_DESCRIPTION("i.MX8 SCU OCOTP fuse box driver");
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MODULE_LICENSE("GPL v2");
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