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4f352d1fc5
i.MX TPM needs "ipg" clock for register access and "per" clock for timer function, the driver gets "ipg" clock by searching the clock name, but timer-of initialization will get first clock in device tree TPM node since no clock name specified in of_clk, that means the "per" clock MUST be the first clock entry in device tree TPM node, this patch specifies clock name for of_clk to avoid this restriction, it makes TPM driver work properly with different sequence of clock entries in device tree TPM node. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
235 lines
5.5 KiB
C
235 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2016 Freescale Semiconductor, Inc.
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// Copyright 2017 NXP
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include "timer-of.h"
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#define TPM_PARAM 0x4
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#define TPM_PARAM_WIDTH_SHIFT 16
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#define TPM_PARAM_WIDTH_MASK (0xff << 16)
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#define TPM_SC 0x10
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#define TPM_SC_CMOD_INC_PER_CNT (0x1 << 3)
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#define TPM_SC_CMOD_DIV_DEFAULT 0x3
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#define TPM_SC_CMOD_DIV_MAX 0x7
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#define TPM_SC_TOF_MASK (0x1 << 7)
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#define TPM_CNT 0x14
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#define TPM_MOD 0x18
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#define TPM_STATUS 0x1c
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#define TPM_STATUS_CH0F BIT(0)
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#define TPM_C0SC 0x20
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#define TPM_C0SC_CHIE BIT(6)
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#define TPM_C0SC_MODE_SHIFT 2
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#define TPM_C0SC_MODE_MASK 0x3c
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#define TPM_C0SC_MODE_SW_COMPARE 0x4
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#define TPM_C0SC_CHF_MASK (0x1 << 7)
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#define TPM_C0V 0x24
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static int counter_width;
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static void __iomem *timer_base;
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static inline void tpm_timer_disable(void)
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{
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unsigned int val;
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/* channel disable */
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val = readl(timer_base + TPM_C0SC);
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val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE);
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writel(val, timer_base + TPM_C0SC);
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}
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static inline void tpm_timer_enable(void)
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{
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unsigned int val;
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/* channel enabled in sw compare mode */
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val = readl(timer_base + TPM_C0SC);
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val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) |
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TPM_C0SC_CHIE;
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writel(val, timer_base + TPM_C0SC);
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}
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static inline void tpm_irq_acknowledge(void)
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{
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writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
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}
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static struct delay_timer tpm_delay_timer;
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static inline unsigned long tpm_read_counter(void)
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{
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return readl(timer_base + TPM_CNT);
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}
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static unsigned long tpm_read_current_timer(void)
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{
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return tpm_read_counter();
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}
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static u64 notrace tpm_read_sched_clock(void)
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{
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return tpm_read_counter();
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}
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static int tpm_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned long next, now;
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next = tpm_read_counter();
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next += delta;
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writel(next, timer_base + TPM_C0V);
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now = tpm_read_counter();
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/*
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* NOTE: We observed in a very small probability, the bus fabric
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* contention between GPU and A7 may results a few cycles delay
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* of writing CNT registers which may cause the min_delta event got
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* missed, so we need add a ETIME check here in case it happened.
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*/
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return (int)(next - now) <= 0 ? -ETIME : 0;
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}
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static int tpm_set_state_oneshot(struct clock_event_device *evt)
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{
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tpm_timer_enable();
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return 0;
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}
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static int tpm_set_state_shutdown(struct clock_event_device *evt)
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{
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tpm_timer_disable();
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return 0;
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}
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static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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tpm_irq_acknowledge();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct timer_of to_tpm = {
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.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "i.MX7ULP TPM Timer",
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.rating = 200,
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = tpm_set_state_shutdown,
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.set_state_oneshot = tpm_set_state_oneshot,
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.set_next_event = tpm_set_next_event,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.handler = tpm_timer_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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.of_clk = {
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.name = "per",
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},
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};
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static int __init tpm_clocksource_init(void)
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{
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tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
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tpm_delay_timer.freq = timer_of_rate(&to_tpm) >> 3;
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register_current_timer_delay(&tpm_delay_timer);
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sched_clock_register(tpm_read_sched_clock, counter_width,
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timer_of_rate(&to_tpm) >> 3);
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return clocksource_mmio_init(timer_base + TPM_CNT,
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"imx-tpm",
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timer_of_rate(&to_tpm) >> 3,
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to_tpm.clkevt.rating,
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counter_width,
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clocksource_mmio_readl_up);
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}
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static void __init tpm_clockevent_init(void)
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{
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clockevents_config_and_register(&to_tpm.clkevt,
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timer_of_rate(&to_tpm) >> 3,
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300,
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GENMASK(counter_width - 1,
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1));
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}
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static int __init tpm_timer_init(struct device_node *np)
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{
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struct clk *ipg;
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int ret;
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ipg = of_clk_get_by_name(np, "ipg");
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if (IS_ERR(ipg)) {
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pr_err("tpm: failed to get ipg clk\n");
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return -ENODEV;
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}
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/* enable clk before accessing registers */
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ret = clk_prepare_enable(ipg);
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if (ret) {
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pr_err("tpm: ipg clock enable failed (%d)\n", ret);
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clk_put(ipg);
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return ret;
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}
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ret = timer_of_init(np, &to_tpm);
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if (ret)
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return ret;
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timer_base = timer_of_base(&to_tpm);
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counter_width = (readl(timer_base + TPM_PARAM)
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& TPM_PARAM_WIDTH_MASK) >> TPM_PARAM_WIDTH_SHIFT;
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/* use rating 200 for 32-bit counter and 150 for 16-bit counter */
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to_tpm.clkevt.rating = counter_width == 0x20 ? 200 : 150;
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/*
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* Initialize tpm module to a known state
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* 1) Counter disabled
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* 2) TPM counter operates in up counting mode
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* 3) Timer Overflow Interrupt disabled
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* 4) Channel0 disabled
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* 5) DMA transfers disabled
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*/
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/* make sure counter is disabled */
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writel(0, timer_base + TPM_SC);
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/* TOF is W1C */
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writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);
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writel(0, timer_base + TPM_CNT);
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/* CHF is W1C */
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writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);
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/*
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* increase per cnt,
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* div 8 for 32-bit counter and div 128 for 16-bit counter
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*/
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writel(TPM_SC_CMOD_INC_PER_CNT |
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(counter_width == 0x20 ?
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TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX),
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timer_base + TPM_SC);
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/* set MOD register to maximum for free running mode */
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writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD);
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tpm_clockevent_init();
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return tpm_clocksource_init();
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}
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TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);
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