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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
330 lines
7.6 KiB
C
330 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2011-2012 Calxeda, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define HB_PLL_LOCK_500 0x20000000
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#define HB_PLL_LOCK 0x10000000
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#define HB_PLL_DIVF_SHIFT 20
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#define HB_PLL_DIVF_MASK 0x0ff00000
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#define HB_PLL_DIVQ_SHIFT 16
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#define HB_PLL_DIVQ_MASK 0x00070000
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#define HB_PLL_DIVR_SHIFT 8
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#define HB_PLL_DIVR_MASK 0x00001f00
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#define HB_PLL_RANGE_SHIFT 4
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#define HB_PLL_RANGE_MASK 0x00000070
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#define HB_PLL_BYPASS 0x00000008
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#define HB_PLL_RESET 0x00000004
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#define HB_PLL_EXT_BYPASS 0x00000002
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#define HB_PLL_EXT_ENA 0x00000001
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#define HB_PLL_VCO_MIN_FREQ 2133000000
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#define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
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#define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
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#define HB_A9_BCLK_DIV_MASK 0x00000006
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#define HB_A9_BCLK_DIV_SHIFT 1
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#define HB_A9_PCLK_DIV 0x00000001
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struct hb_clk {
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struct clk_hw hw;
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void __iomem *reg;
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char *parent_name;
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};
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#define to_hb_clk(p) container_of(p, struct hb_clk, hw)
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static int clk_pll_prepare(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg &= ~HB_PLL_RESET;
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writel(reg, hbclk->reg);
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while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
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;
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while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
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;
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return 0;
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}
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static void clk_pll_unprepare(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg |= HB_PLL_RESET;
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writel(reg, hbclk->reg);
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}
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static int clk_pll_enable(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg |= HB_PLL_EXT_ENA;
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writel(reg, hbclk->reg);
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return 0;
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}
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static void clk_pll_disable(struct clk_hw *hwclk)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 reg;
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reg = readl(hbclk->reg);
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reg &= ~HB_PLL_EXT_ENA;
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writel(reg, hbclk->reg);
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}
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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unsigned long divf, divq, vco_freq, reg;
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reg = readl(hbclk->reg);
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if (reg & HB_PLL_EXT_BYPASS)
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return parent_rate;
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divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
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divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
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vco_freq = parent_rate * (divf + 1);
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return vco_freq / (1 << divq);
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}
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static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
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u32 *pdivq, u32 *pdivf)
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{
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u32 divq, divf;
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unsigned long vco_freq;
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if (rate < HB_PLL_MIN_FREQ)
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rate = HB_PLL_MIN_FREQ;
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if (rate > HB_PLL_MAX_FREQ)
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rate = HB_PLL_MAX_FREQ;
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for (divq = 1; divq <= 6; divq++) {
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if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
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break;
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}
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vco_freq = rate * (1 << divq);
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divf = (vco_freq + (ref_freq / 2)) / ref_freq;
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divf--;
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*pdivq = divq;
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*pdivf = divf;
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}
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static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long *parent_rate)
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{
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u32 divq, divf;
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unsigned long ref_freq = *parent_rate;
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clk_pll_calc(rate, ref_freq, &divq, &divf);
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return (ref_freq * (divf + 1)) / (1 << divq);
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}
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static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 divq, divf;
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u32 reg;
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clk_pll_calc(rate, parent_rate, &divq, &divf);
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reg = readl(hbclk->reg);
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if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
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/* Need to re-lock PLL, so put it into bypass mode */
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reg |= HB_PLL_EXT_BYPASS;
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writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
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writel(reg | HB_PLL_RESET, hbclk->reg);
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reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
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reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
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writel(reg | HB_PLL_RESET, hbclk->reg);
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writel(reg, hbclk->reg);
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while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
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;
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while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
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;
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reg |= HB_PLL_EXT_ENA;
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reg &= ~HB_PLL_EXT_BYPASS;
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} else {
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writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
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reg &= ~HB_PLL_DIVQ_MASK;
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reg |= divq << HB_PLL_DIVQ_SHIFT;
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writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
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}
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writel(reg, hbclk->reg);
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return 0;
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}
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static const struct clk_ops clk_pll_ops = {
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.prepare = clk_pll_prepare,
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.unprepare = clk_pll_unprepare,
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.enable = clk_pll_enable,
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.disable = clk_pll_disable,
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.recalc_rate = clk_pll_recalc_rate,
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.round_rate = clk_pll_round_rate,
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.set_rate = clk_pll_set_rate,
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};
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static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
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return parent_rate / div;
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}
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static const struct clk_ops a9periphclk_ops = {
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.recalc_rate = clk_cpu_periphclk_recalc_rate,
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};
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static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
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return parent_rate / (div + 2);
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}
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static const struct clk_ops a9bclk_ops = {
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.recalc_rate = clk_cpu_a9bclk_recalc_rate,
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};
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static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 div;
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div = readl(hbclk->reg) & 0x1f;
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div++;
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div *= 2;
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return parent_rate / div;
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}
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static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long *parent_rate)
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{
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u32 div;
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div = *parent_rate / rate;
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div++;
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div &= ~0x1;
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return *parent_rate / div;
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}
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static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct hb_clk *hbclk = to_hb_clk(hwclk);
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u32 div;
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div = parent_rate / rate;
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if (div & 0x1)
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return -EINVAL;
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writel(div >> 1, hbclk->reg);
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return 0;
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}
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static const struct clk_ops periclk_ops = {
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.recalc_rate = clk_periclk_recalc_rate,
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.round_rate = clk_periclk_round_rate,
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.set_rate = clk_periclk_set_rate,
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};
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static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags)
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{
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u32 reg;
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struct hb_clk *hb_clk;
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const char *clk_name = node->name;
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const char *parent_name;
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struct clk_init_data init;
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struct device_node *srnp;
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int rc;
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rc = of_property_read_u32(node, "reg", ®);
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if (WARN_ON(rc))
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return;
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hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
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if (WARN_ON(!hb_clk))
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return;
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/* Map system registers */
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srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
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hb_clk->reg = of_iomap(srnp, 0);
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of_node_put(srnp);
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BUG_ON(!hb_clk->reg);
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hb_clk->reg += reg;
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = ops;
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init.flags = clkflags;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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hb_clk->hw.init = &init;
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rc = clk_hw_register(NULL, &hb_clk->hw);
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if (WARN_ON(rc)) {
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kfree(hb_clk);
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return;
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}
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
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}
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static void __init hb_pll_init(struct device_node *node)
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{
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hb_clk_init(node, &clk_pll_ops, 0);
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}
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CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
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static void __init hb_a9periph_init(struct device_node *node)
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{
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hb_clk_init(node, &a9periphclk_ops, 0);
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}
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CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
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static void __init hb_a9bus_init(struct device_node *node)
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{
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hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL);
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}
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CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
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static void __init hb_emmc_init(struct device_node *node)
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{
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hb_clk_init(node, &periclk_ops, 0);
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}
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CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
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