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641e97f318
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
57 lines
1.4 KiB
C
57 lines
1.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
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#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_fpu 1
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#define cpu_has_32fpr 1
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#define cpu_has_counter 1
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#define cpu_has_watch 0
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_prefetch 0
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#define cpu_has_mcheck 0
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#define cpu_has_ejtag 0
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#define cpu_has_inclusive_pcaches 0
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#define cpu_dcache_line_size() 32
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#define cpu_icache_line_size() 32
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#define cpu_scache_line_size() 0
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#ifdef CONFIG_64BIT
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#define cpu_has_llsc 0
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#else
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#define cpu_has_llsc 1
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#endif
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#define cpu_has_mips16 0
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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#define cpu_has_vtag_icache 0
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#define cpu_has_ic_fills_f_dc 0
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#define cpu_icache_snoops_remote_store 0
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#define cpu_has_dsp 0
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#define cpu_has_mipsmt 0
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#define cpu_has_userlocal 0
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#define cpu_has_mips32r1 0
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
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