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bab588fcfb
This is a larger set of new functionality for the existing SoC families,
including:
* vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850
* prima2 gains support for the "marco" SoC family, its SMP based cousin
* tegra gains support for the new Tegra4 (Tegra114) family
* socfpga now supports a newer version of the hardware including SMP
* i.mx31 and bcm2835 are now using DT probing for their clocks
* lots of updates for sh-mobile
* OMAP updates for clocks, power management and USB
* i.mx6q and tegra now support cpuidle
* kirkwood now supports PCIe hot plugging
* tegra clock support is updated
* tegra USB PHY probing gets implemented diffently
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann:
"This is a larger set of new functionality for the existing SoC
families, including:
- vt8500 gains support for new CPU cores, notably the Cortex-A9 based
wm8850
- prima2 gains support for the "marco" SoC family, its SMP based
cousin
- tegra gains support for the new Tegra4 (Tegra114) family
- socfpga now supports a newer version of the hardware including SMP
- i.mx31 and bcm2835 are now using DT probing for their clocks
- lots of updates for sh-mobile
- OMAP updates for clocks, power management and USB
- i.mx6q and tegra now support cpuidle
- kirkwood now supports PCIe hot plugging
- tegra clock support is updated
- tegra USB PHY probing gets implemented diffently"
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
ARM: prima2: remove duplicate v7_invalidate_l1
ARM: shmobile: r8a7779: Correct TMU clock support again
ARM: prima2: fix __init section for cpu hotplug
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
ARM: tegra: Fix build error for gic update
ARM: tegra: remove empty tegra_smp_init_cpus()
ARM: shmobile: Register ARM architected timer
ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
ARM: shmobile: r8a7779: Correct TMU clock support
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
...
389 lines
8.9 KiB
C
389 lines
8.9 KiB
C
/*
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* r8a7779 processor support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_intc.h>
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#include <linux/sh_timer.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/r8a7779.h>
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#include <mach/common.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <asm/hardware/cache-l2x0.h>
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static struct map_desc r8a7779_io_desc[] __initdata = {
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/* 2M entity map for 0xf0000000 (MPCORE) */
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{
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.virtual = 0xf0000000,
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.pfn = __phys_to_pfn(0xf0000000),
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.length = SZ_2M,
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.type = MT_DEVICE_NONSHARED
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},
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/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
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{
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0xfe000000),
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.length = SZ_16M,
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.type = MT_DEVICE_NONSHARED
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},
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};
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void __init r8a7779_map_io(void)
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{
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iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
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}
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static struct resource r8a7779_pfc_resources[] = {
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[0] = {
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.start = 0xfffc0000,
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.end = 0xfffc023b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 0xffc40000,
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.end = 0xffc46fff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device r8a7779_pfc_device = {
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.name = "pfc-r8a7779",
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.id = -1,
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.resource = r8a7779_pfc_resources,
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.num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
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};
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void __init r8a7779_pinmux_init(void)
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{
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platform_device_register(&r8a7779_pfc_device);
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}
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xffe40000,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = SCIx_IRQ_MUXED(gic_spi(88)),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xffe41000,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = SCIx_IRQ_MUXED(gic_spi(89)),
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xffe42000,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = SCIx_IRQ_MUXED(gic_spi(90)),
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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static struct plat_sci_port scif3_platform_data = {
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.mapbase = 0xffe43000,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = SCIx_IRQ_MUXED(gic_spi(91)),
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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static struct plat_sci_port scif4_platform_data = {
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.mapbase = 0xffe44000,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = SCIx_IRQ_MUXED(gic_spi(92)),
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};
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static struct platform_device scif4_device = {
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.name = "sh-sci",
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.id = 4,
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.dev = {
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.platform_data = &scif4_platform_data,
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},
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};
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static struct plat_sci_port scif5_platform_data = {
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.mapbase = 0xffe45000,
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
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.scbrr_algo_id = SCBRR_ALGO_2,
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.type = PORT_SCIF,
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.irqs = SCIx_IRQ_MUXED(gic_spi(93)),
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};
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static struct platform_device scif5_device = {
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.name = "sh-sci",
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.id = 5,
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.dev = {
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.platform_data = &scif5_platform_data,
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},
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};
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/* TMU */
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static struct sh_timer_config tmu00_platform_data = {
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.name = "TMU00",
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.channel_offset = 0x4,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource tmu00_resources[] = {
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[0] = {
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.name = "TMU00",
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.start = 0xffd80008,
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.end = 0xffd80013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_spi(32),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu00_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu00_platform_data,
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},
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.resource = tmu00_resources,
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.num_resources = ARRAY_SIZE(tmu00_resources),
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};
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static struct sh_timer_config tmu01_platform_data = {
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.name = "TMU01",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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static struct resource tmu01_resources[] = {
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[0] = {
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.name = "TMU01",
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.start = 0xffd80014,
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.end = 0xffd8001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_spi(33),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu01_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu01_platform_data,
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},
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.resource = tmu01_resources,
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.num_resources = ARRAY_SIZE(tmu01_resources),
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};
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/* I2C */
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static struct resource rcar_i2c0_res[] = {
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{
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.start = 0xffc70000,
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.end = 0xffc70fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_spi(79),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c0_device = {
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.name = "i2c-rcar",
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.id = 0,
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.resource = rcar_i2c0_res,
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.num_resources = ARRAY_SIZE(rcar_i2c0_res),
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};
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static struct resource rcar_i2c1_res[] = {
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{
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.start = 0xffc71000,
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.end = 0xffc71fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_spi(82),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c1_device = {
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.name = "i2c-rcar",
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.id = 1,
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.resource = rcar_i2c1_res,
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.num_resources = ARRAY_SIZE(rcar_i2c1_res),
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};
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static struct resource rcar_i2c2_res[] = {
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{
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.start = 0xffc72000,
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.end = 0xffc72fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_spi(80),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c2_device = {
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.name = "i2c-rcar",
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.id = 2,
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.resource = rcar_i2c2_res,
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.num_resources = ARRAY_SIZE(rcar_i2c2_res),
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};
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static struct resource rcar_i2c3_res[] = {
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{
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.start = 0xffc73000,
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.end = 0xffc73fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = gic_spi(81),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c3_device = {
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.name = "i2c-rcar",
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.id = 3,
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.resource = rcar_i2c3_res,
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.num_resources = ARRAY_SIZE(rcar_i2c3_res),
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};
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static struct platform_device *r8a7779_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&scif4_device,
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&scif5_device,
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&tmu00_device,
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&tmu01_device,
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&i2c0_device,
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&i2c1_device,
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&i2c2_device,
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&i2c3_device,
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};
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static struct platform_device *r8a7779_late_devices[] __initdata = {
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};
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void __init r8a7779_add_standard_devices(void)
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{
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#ifdef CONFIG_CACHE_L2X0
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/* Early BRESP enable, Shared attribute override enable, 64K*16way */
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l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
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#endif
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r8a7779_pm_init();
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r8a7779_init_pm_domains();
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platform_add_devices(r8a7779_early_devices,
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ARRAY_SIZE(r8a7779_early_devices));
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platform_add_devices(r8a7779_late_devices,
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ARRAY_SIZE(r8a7779_late_devices));
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}
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/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
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void __init __weak r8a7779_register_twd(void) { }
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void __init r8a7779_earlytimer_init(void)
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{
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r8a7779_clock_init();
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shmobile_earlytimer_init();
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r8a7779_register_twd();
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}
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void __init r8a7779_add_early_devices(void)
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{
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early_platform_add_devices(r8a7779_early_devices,
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ARRAY_SIZE(r8a7779_early_devices));
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/* Early serial console setup is not included here due to
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* memory map collisions. The SCIF serial ports in r8a7779
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* are difficult to entity map 1:1 due to collision with the
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* virtual memory range used by the coherent DMA code on ARM.
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*
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* Anyone wanting to debug early can remove UPF_IOREMAP from
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* the sh-sci serial console platform data, adjust mapbase
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* to a static M:N virt:phys mapping that needs to be added to
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* the mappings passed with iotable_init() above.
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*
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* Then add a call to shmobile_setup_console() from this function.
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*
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* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
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* command line in case of the marzen board.
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*/
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}
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