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2c941a2040
This updates the sparc64 iommu/pci dma mappers to sg chaining. Acked-by: David S. Miller <davem@davemloft.net> Later updated to newer kernel with unified sparc64 iommu sg handling. Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
1071 lines
25 KiB
C
1071 lines
25 KiB
C
/* pci_sun4v.c: SUN4V specific PCI controller support.
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*
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* Copyright (C) 2006, 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/log2.h>
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#include <linux/scatterlist.h>
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#include <asm/iommu.h>
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#include <asm/irq.h>
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#include <asm/upa.h>
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#include <asm/pstate.h>
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#include <asm/oplib.h>
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#include <asm/hypervisor.h>
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#include <asm/prom.h>
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#include "pci_impl.h"
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#include "iommu_common.h"
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#include "pci_sun4v.h"
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static unsigned long vpci_major = 1;
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static unsigned long vpci_minor = 1;
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#define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
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struct iommu_batch {
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struct device *dev; /* Device mapping is for. */
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unsigned long prot; /* IOMMU page protections */
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unsigned long entry; /* Index into IOTSB. */
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u64 *pglist; /* List of physical pages */
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unsigned long npages; /* Number of pages in list. */
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};
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static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
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/* Interrupts must be disabled. */
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static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
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{
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struct iommu_batch *p = &__get_cpu_var(iommu_batch);
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p->dev = dev;
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p->prot = prot;
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p->entry = entry;
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p->npages = 0;
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}
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/* Interrupts must be disabled. */
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static long iommu_batch_flush(struct iommu_batch *p)
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{
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struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
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unsigned long devhandle = pbm->devhandle;
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unsigned long prot = p->prot;
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unsigned long entry = p->entry;
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u64 *pglist = p->pglist;
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unsigned long npages = p->npages;
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while (npages != 0) {
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long num;
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num = pci_sun4v_iommu_map(devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist));
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if (unlikely(num < 0)) {
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if (printk_ratelimit())
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printk("iommu_batch_flush: IOMMU map of "
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"[%08lx:%08lx:%lx:%lx:%lx] failed with "
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"status %ld\n",
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devhandle, HV_PCI_TSBID(0, entry),
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npages, prot, __pa(pglist), num);
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return -1;
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}
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entry += num;
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npages -= num;
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pglist += num;
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}
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p->entry = entry;
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p->npages = 0;
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return 0;
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}
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/* Interrupts must be disabled. */
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static inline long iommu_batch_add(u64 phys_page)
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{
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struct iommu_batch *p = &__get_cpu_var(iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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p->pglist[p->npages++] = phys_page;
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if (p->npages == PGLIST_NENTS)
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return iommu_batch_flush(p);
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return 0;
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}
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/* Interrupts must be disabled. */
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static inline long iommu_batch_end(void)
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{
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struct iommu_batch *p = &__get_cpu_var(iommu_batch);
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BUG_ON(p->npages >= PGLIST_NENTS);
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return iommu_batch_flush(p);
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}
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static long arena_alloc(struct iommu_arena *arena, unsigned long npages)
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{
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unsigned long n, i, start, end, limit;
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int pass;
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limit = arena->limit;
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start = arena->hint;
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pass = 0;
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again:
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n = find_next_zero_bit(arena->map, limit, start);
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end = n + npages;
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if (unlikely(end >= limit)) {
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if (likely(pass < 1)) {
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limit = start;
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start = 0;
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pass++;
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goto again;
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} else {
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/* Scanned the whole thing, give up. */
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return -1;
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}
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}
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for (i = n; i < end; i++) {
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if (test_bit(i, arena->map)) {
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start = i + 1;
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goto again;
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}
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}
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for (i = n; i < end; i++)
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__set_bit(i, arena->map);
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arena->hint = end;
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return n;
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}
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static void arena_free(struct iommu_arena *arena, unsigned long base,
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unsigned long npages)
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{
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unsigned long i;
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for (i = base; i < (base + npages); i++)
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__clear_bit(i, arena->map);
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}
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static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addrp, gfp_t gfp)
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{
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struct iommu *iommu;
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unsigned long flags, order, first_page, npages, n;
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void *ret;
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long entry;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (unlikely(order >= MAX_ORDER))
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return NULL;
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npages = size >> IO_PAGE_SHIFT;
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first_page = __get_free_pages(gfp, order);
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if (unlikely(first_page == 0UL))
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return NULL;
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = dev->archdata.iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto arena_alloc_fail;
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*dma_addrp = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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first_page = __pa(first_page);
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local_irq_save(flags);
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iommu_batch_start(dev,
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(HV_PCI_MAP_ATTR_READ |
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HV_PCI_MAP_ATTR_WRITE),
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entry);
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for (n = 0; n < npages; n++) {
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long err = iommu_batch_add(first_page + (n * PAGE_SIZE));
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(iommu_batch_end() < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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return ret;
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iommu_map_fail:
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/* Interrupts are disabled. */
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spin_lock(&iommu->lock);
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arena_free(&iommu->arena, entry, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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arena_alloc_fail:
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free_pages(first_page, order);
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return NULL;
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}
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static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
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dma_addr_t dvma)
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{
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struct pci_pbm_info *pbm;
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struct iommu *iommu;
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unsigned long flags, order, npages, entry;
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u32 devhandle;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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pbm = dev->archdata.host_controller;
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devhandle = pbm->devhandle;
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entry = ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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arena_free(&iommu->arena, entry, npages);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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static dma_addr_t dma_4v_map_single(struct device *dev, void *ptr, size_t sz,
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enum dma_data_direction direction)
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{
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struct iommu *iommu;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr;
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u32 bus_addr, ret;
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unsigned long prot;
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long entry;
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iommu = dev->archdata.iommu;
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if (unlikely(direction == DMA_NONE))
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goto bad;
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oaddr = (unsigned long)ptr;
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != DMA_TO_DEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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local_irq_save(flags);
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iommu_batch_start(dev, prot, entry);
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for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
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long err = iommu_batch_add(base_paddr);
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if (unlikely(err < 0L))
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goto iommu_map_fail;
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}
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if (unlikely(iommu_batch_end() < 0L))
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goto iommu_map_fail;
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local_irq_restore(flags);
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return ret;
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bad:
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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iommu_map_fail:
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/* Interrupts are disabled. */
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spin_lock(&iommu->lock);
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arena_free(&iommu->arena, entry, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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return DMA_ERROR_CODE;
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}
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static void dma_4v_unmap_single(struct device *dev, dma_addr_t bus_addr,
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size_t sz, enum dma_data_direction direction)
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{
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struct pci_pbm_info *pbm;
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struct iommu *iommu;
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unsigned long flags, npages;
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long entry;
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u32 devhandle;
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if (unlikely(direction == DMA_NONE)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return;
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}
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iommu = dev->archdata.iommu;
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pbm = dev->archdata.host_controller;
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devhandle = pbm->devhandle;
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npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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bus_addr &= IO_PAGE_MASK;
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spin_lock_irqsave(&iommu->lock, flags);
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entry = (bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
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arena_free(&iommu->arena, entry, npages);
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do {
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unsigned long num;
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num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
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npages);
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entry += num;
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npages -= num;
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} while (npages != 0);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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#define SG_ENT_PHYS_ADDRESS(SG) \
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(__pa(page_address((SG)->page)) + (SG)->offset)
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static inline long fill_sg(long entry, struct device *dev,
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struct scatterlist *sg,
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int nused, int nelems, unsigned long prot)
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{
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struct scatterlist *dma_sg = sg;
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struct scatterlist *sg_end = sg_last(sg, nelems);
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unsigned long flags;
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int i;
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local_irq_save(flags);
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iommu_batch_start(dev, prot, entry);
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for (i = 0; i < nused; i++) {
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unsigned long pteval = ~0UL;
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u32 dma_npages;
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dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
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dma_sg->dma_length +
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((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
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do {
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unsigned long offset;
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signed int len;
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/* If we are here, we know we have at least one
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* more page to map. So walk forward until we
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* hit a page crossing, and begin creating new
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* mappings from that spot.
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*/
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for (;;) {
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unsigned long tmp;
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tmp = SG_ENT_PHYS_ADDRESS(sg);
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len = sg->length;
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if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = tmp & IO_PAGE_MASK;
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offset = tmp & (IO_PAGE_SIZE - 1UL);
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break;
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}
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if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
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offset = 0UL;
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len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
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break;
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}
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sg = sg_next(sg);
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}
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pteval = (pteval & IOPTE_PAGE);
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while (len > 0) {
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long err;
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err = iommu_batch_add(pteval);
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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pteval += IO_PAGE_SIZE;
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len -= (IO_PAGE_SIZE - offset);
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offset = 0;
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dma_npages--;
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}
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pteval = (pteval & IOPTE_PAGE) + len;
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sg = sg_next(sg);
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/* Skip over any tail mappings we've fully mapped,
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* adjusting pteval along the way. Stop when we
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* detect a page crossing event.
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*/
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while ((pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
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(pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
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((pteval ^
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(SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
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pteval += sg->length;
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if (sg == sg_end)
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break;
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sg = sg_next(sg);
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}
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if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
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pteval = ~0UL;
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} while (dma_npages != 0);
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dma_sg = sg_next(dma_sg);
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}
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if (unlikely(iommu_batch_end() < 0L))
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goto iommu_map_failed;
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local_irq_restore(flags);
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return 0;
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iommu_map_failed:
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local_irq_restore(flags);
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return -1L;
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}
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static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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struct iommu *iommu;
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unsigned long flags, npages, prot;
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u32 dma_base;
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struct scatterlist *sgtmp;
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long entry, err;
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int used;
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/* Fast path single entry scatterlists. */
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if (nelems == 1) {
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sglist->dma_address =
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dma_4v_map_single(dev,
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(page_address(sglist->page) +
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sglist->offset),
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sglist->length, direction);
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if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
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return 0;
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sglist->dma_length = sglist->length;
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return 1;
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}
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iommu = dev->archdata.iommu;
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if (unlikely(direction == DMA_NONE))
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goto bad;
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/* Step 1: Prepare scatter list. */
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npages = prepare_sg(sglist, nelems);
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/* Step 2: Allocate a cluster and context, if necessary. */
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spin_lock_irqsave(&iommu->lock, flags);
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entry = arena_alloc(&iommu->arena, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(entry < 0L))
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goto bad;
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dma_base = iommu->page_table_map_base +
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(entry << IO_PAGE_SHIFT);
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/* Step 3: Normalize DMA addresses. */
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used = nelems;
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sgtmp = sglist;
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while (used && sgtmp->dma_length) {
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sgtmp->dma_address += dma_base;
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sgtmp = sg_next(sgtmp);
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used--;
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}
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used = nelems - used;
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/* Step 4: Create the mappings. */
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prot = HV_PCI_MAP_ATTR_READ;
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if (direction != DMA_TO_DEVICE)
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prot |= HV_PCI_MAP_ATTR_WRITE;
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err = fill_sg(entry, dev, sglist, used, nelems, prot);
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if (unlikely(err < 0L))
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goto iommu_map_failed;
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return used;
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bad:
|
|
if (printk_ratelimit())
|
|
WARN_ON(1);
|
|
return 0;
|
|
|
|
iommu_map_failed:
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
arena_free(&iommu->arena, entry, npages);
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|
int nelems, enum dma_data_direction direction)
|
|
{
|
|
struct pci_pbm_info *pbm;
|
|
struct iommu *iommu;
|
|
unsigned long flags, i, npages;
|
|
struct scatterlist *sg, *sgprv;
|
|
long entry;
|
|
u32 devhandle, bus_addr;
|
|
|
|
if (unlikely(direction == DMA_NONE)) {
|
|
if (printk_ratelimit())
|
|
WARN_ON(1);
|
|
}
|
|
|
|
iommu = dev->archdata.iommu;
|
|
pbm = dev->archdata.host_controller;
|
|
devhandle = pbm->devhandle;
|
|
|
|
bus_addr = sglist->dma_address & IO_PAGE_MASK;
|
|
sgprv = NULL;
|
|
for_each_sg(sglist, sg, nelems, i) {
|
|
if (sg->dma_length == 0)
|
|
break;
|
|
|
|
sgprv = sg;
|
|
}
|
|
|
|
npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) -
|
|
bus_addr) >> IO_PAGE_SHIFT;
|
|
|
|
entry = ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
arena_free(&iommu->arena, entry, npages);
|
|
|
|
do {
|
|
unsigned long num;
|
|
|
|
num = pci_sun4v_iommu_demap(devhandle, HV_PCI_TSBID(0, entry),
|
|
npages);
|
|
entry += num;
|
|
npages -= num;
|
|
} while (npages != 0);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void dma_4v_sync_single_for_cpu(struct device *dev,
|
|
dma_addr_t bus_addr, size_t sz,
|
|
enum dma_data_direction direction)
|
|
{
|
|
/* Nothing to do... */
|
|
}
|
|
|
|
static void dma_4v_sync_sg_for_cpu(struct device *dev,
|
|
struct scatterlist *sglist, int nelems,
|
|
enum dma_data_direction direction)
|
|
{
|
|
/* Nothing to do... */
|
|
}
|
|
|
|
const struct dma_ops sun4v_dma_ops = {
|
|
.alloc_coherent = dma_4v_alloc_coherent,
|
|
.free_coherent = dma_4v_free_coherent,
|
|
.map_single = dma_4v_map_single,
|
|
.unmap_single = dma_4v_unmap_single,
|
|
.map_sg = dma_4v_map_sg,
|
|
.unmap_sg = dma_4v_unmap_sg,
|
|
.sync_single_for_cpu = dma_4v_sync_single_for_cpu,
|
|
.sync_sg_for_cpu = dma_4v_sync_sg_for_cpu,
|
|
};
|
|
|
|
static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm)
|
|
{
|
|
struct property *prop;
|
|
struct device_node *dp;
|
|
|
|
dp = pbm->prom_node;
|
|
prop = of_find_property(dp, "66mhz-capable", NULL);
|
|
pbm->is_66mhz_capable = (prop != NULL);
|
|
pbm->pci_bus = pci_scan_one_pbm(pbm);
|
|
|
|
/* XXX register error interrupt handlers XXX */
|
|
}
|
|
|
|
static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
|
|
struct iommu *iommu)
|
|
{
|
|
struct iommu_arena *arena = &iommu->arena;
|
|
unsigned long i, cnt = 0;
|
|
u32 devhandle;
|
|
|
|
devhandle = pbm->devhandle;
|
|
for (i = 0; i < arena->limit; i++) {
|
|
unsigned long ret, io_attrs, ra;
|
|
|
|
ret = pci_sun4v_iommu_getmap(devhandle,
|
|
HV_PCI_TSBID(0, i),
|
|
&io_attrs, &ra);
|
|
if (ret == HV_EOK) {
|
|
if (page_in_phys_avail(ra)) {
|
|
pci_sun4v_iommu_demap(devhandle,
|
|
HV_PCI_TSBID(0, i), 1);
|
|
} else {
|
|
cnt++;
|
|
__set_bit(i, arena->map);
|
|
}
|
|
}
|
|
}
|
|
|
|
return cnt;
|
|
}
|
|
|
|
static void pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
|
|
{
|
|
struct iommu *iommu = pbm->iommu;
|
|
struct property *prop;
|
|
unsigned long num_tsb_entries, sz, tsbsize;
|
|
u32 vdma[2], dma_mask, dma_offset;
|
|
|
|
prop = of_find_property(pbm->prom_node, "virtual-dma", NULL);
|
|
if (prop) {
|
|
u32 *val = prop->value;
|
|
|
|
vdma[0] = val[0];
|
|
vdma[1] = val[1];
|
|
} else {
|
|
/* No property, use default values. */
|
|
vdma[0] = 0x80000000;
|
|
vdma[1] = 0x80000000;
|
|
}
|
|
|
|
if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
|
|
prom_printf("PCI-SUN4V: strange virtual-dma[%08x:%08x].\n",
|
|
vdma[0], vdma[1]);
|
|
prom_halt();
|
|
};
|
|
|
|
dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
|
|
num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
|
|
tsbsize = num_tsb_entries * sizeof(iopte_t);
|
|
|
|
dma_offset = vdma[0];
|
|
|
|
/* Setup initial software IOMMU state. */
|
|
spin_lock_init(&iommu->lock);
|
|
iommu->ctx_lowest_free = 1;
|
|
iommu->page_table_map_base = dma_offset;
|
|
iommu->dma_addr_mask = dma_mask;
|
|
|
|
/* Allocate and initialize the free area map. */
|
|
sz = (num_tsb_entries + 7) / 8;
|
|
sz = (sz + 7UL) & ~7UL;
|
|
iommu->arena.map = kzalloc(sz, GFP_KERNEL);
|
|
if (!iommu->arena.map) {
|
|
prom_printf("PCI_IOMMU: Error, kmalloc(arena.map) failed.\n");
|
|
prom_halt();
|
|
}
|
|
iommu->arena.limit = num_tsb_entries;
|
|
|
|
sz = probe_existing_entries(pbm, iommu);
|
|
if (sz)
|
|
printk("%s: Imported %lu TSB entries from OBP\n",
|
|
pbm->name, sz);
|
|
}
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
struct pci_sun4v_msiq_entry {
|
|
u64 version_type;
|
|
#define MSIQ_VERSION_MASK 0xffffffff00000000UL
|
|
#define MSIQ_VERSION_SHIFT 32
|
|
#define MSIQ_TYPE_MASK 0x00000000000000ffUL
|
|
#define MSIQ_TYPE_SHIFT 0
|
|
#define MSIQ_TYPE_NONE 0x00
|
|
#define MSIQ_TYPE_MSG 0x01
|
|
#define MSIQ_TYPE_MSI32 0x02
|
|
#define MSIQ_TYPE_MSI64 0x03
|
|
#define MSIQ_TYPE_INTX 0x08
|
|
#define MSIQ_TYPE_NONE2 0xff
|
|
|
|
u64 intx_sysino;
|
|
u64 reserved1;
|
|
u64 stick;
|
|
u64 req_id; /* bus/device/func */
|
|
#define MSIQ_REQID_BUS_MASK 0xff00UL
|
|
#define MSIQ_REQID_BUS_SHIFT 8
|
|
#define MSIQ_REQID_DEVICE_MASK 0x00f8UL
|
|
#define MSIQ_REQID_DEVICE_SHIFT 3
|
|
#define MSIQ_REQID_FUNC_MASK 0x0007UL
|
|
#define MSIQ_REQID_FUNC_SHIFT 0
|
|
|
|
u64 msi_address;
|
|
|
|
/* The format of this value is message type dependent.
|
|
* For MSI bits 15:0 are the data from the MSI packet.
|
|
* For MSI-X bits 31:0 are the data from the MSI packet.
|
|
* For MSG, the message code and message routing code where:
|
|
* bits 39:32 is the bus/device/fn of the msg target-id
|
|
* bits 18:16 is the message routing code
|
|
* bits 7:0 is the message code
|
|
* For INTx the low order 2-bits are:
|
|
* 00 - INTA
|
|
* 01 - INTB
|
|
* 10 - INTC
|
|
* 11 - INTD
|
|
*/
|
|
u64 msi_data;
|
|
|
|
u64 reserved2;
|
|
};
|
|
|
|
static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
|
|
unsigned long *head)
|
|
{
|
|
unsigned long err, limit;
|
|
|
|
err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
|
|
if (unlikely(err))
|
|
return -ENXIO;
|
|
|
|
limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
|
|
if (unlikely(*head >= limit))
|
|
return -EFBIG;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
|
|
unsigned long msiqid, unsigned long *head,
|
|
unsigned long *msi)
|
|
{
|
|
struct pci_sun4v_msiq_entry *ep;
|
|
unsigned long err, type;
|
|
|
|
/* Note: void pointer arithmetic, 'head' is a byte offset */
|
|
ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
|
|
(pbm->msiq_ent_count *
|
|
sizeof(struct pci_sun4v_msiq_entry))) +
|
|
*head);
|
|
|
|
if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
|
|
return 0;
|
|
|
|
type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
|
|
if (unlikely(type != MSIQ_TYPE_MSI32 &&
|
|
type != MSIQ_TYPE_MSI64))
|
|
return -EINVAL;
|
|
|
|
*msi = ep->msi_data;
|
|
|
|
err = pci_sun4v_msi_setstate(pbm->devhandle,
|
|
ep->msi_data /* msi_num */,
|
|
HV_MSISTATE_IDLE);
|
|
if (unlikely(err))
|
|
return -ENXIO;
|
|
|
|
/* Clear the entry. */
|
|
ep->version_type &= ~MSIQ_TYPE_MASK;
|
|
|
|
(*head) += sizeof(struct pci_sun4v_msiq_entry);
|
|
if (*head >=
|
|
(pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
|
|
*head = 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
|
|
unsigned long head)
|
|
{
|
|
unsigned long err;
|
|
|
|
err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
|
|
if (unlikely(err))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
|
|
unsigned long msi, int is_msi64)
|
|
{
|
|
if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
|
|
(is_msi64 ?
|
|
HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
|
|
return -ENXIO;
|
|
if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
|
|
return -ENXIO;
|
|
if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
|
|
return -ENXIO;
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
|
|
{
|
|
unsigned long err, msiqid;
|
|
|
|
err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
|
|
if (err)
|
|
return -ENXIO;
|
|
|
|
pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
|
|
{
|
|
unsigned long q_size, alloc_size, pages, order;
|
|
int i;
|
|
|
|
q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
|
|
alloc_size = (pbm->msiq_num * q_size);
|
|
order = get_order(alloc_size);
|
|
pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
|
|
if (pages == 0UL) {
|
|
printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
|
|
order);
|
|
return -ENOMEM;
|
|
}
|
|
memset((char *)pages, 0, PAGE_SIZE << order);
|
|
pbm->msi_queues = (void *) pages;
|
|
|
|
for (i = 0; i < pbm->msiq_num; i++) {
|
|
unsigned long err, base = __pa(pages + (i * q_size));
|
|
unsigned long ret1, ret2;
|
|
|
|
err = pci_sun4v_msiq_conf(pbm->devhandle,
|
|
pbm->msiq_first + i,
|
|
base, pbm->msiq_ent_count);
|
|
if (err) {
|
|
printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
|
|
err);
|
|
goto h_error;
|
|
}
|
|
|
|
err = pci_sun4v_msiq_info(pbm->devhandle,
|
|
pbm->msiq_first + i,
|
|
&ret1, &ret2);
|
|
if (err) {
|
|
printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
|
|
err);
|
|
goto h_error;
|
|
}
|
|
if (ret1 != base || ret2 != pbm->msiq_ent_count) {
|
|
printk(KERN_ERR "MSI: Bogus qconf "
|
|
"expected[%lx:%x] got[%lx:%lx]\n",
|
|
base, pbm->msiq_ent_count,
|
|
ret1, ret2);
|
|
goto h_error;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
h_error:
|
|
free_pages(pages, order);
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
|
|
{
|
|
unsigned long q_size, alloc_size, pages, order;
|
|
int i;
|
|
|
|
for (i = 0; i < pbm->msiq_num; i++) {
|
|
unsigned long msiqid = pbm->msiq_first + i;
|
|
|
|
(void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
|
|
}
|
|
|
|
q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
|
|
alloc_size = (pbm->msiq_num * q_size);
|
|
order = get_order(alloc_size);
|
|
|
|
pages = (unsigned long) pbm->msi_queues;
|
|
|
|
free_pages(pages, order);
|
|
|
|
pbm->msi_queues = NULL;
|
|
}
|
|
|
|
static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
|
|
unsigned long msiqid,
|
|
unsigned long devino)
|
|
{
|
|
unsigned int virt_irq = sun4v_build_irq(pbm->devhandle, devino);
|
|
|
|
if (!virt_irq)
|
|
return -ENOMEM;
|
|
|
|
if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
|
|
return -EINVAL;
|
|
if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
|
|
return -EINVAL;
|
|
|
|
return virt_irq;
|
|
}
|
|
|
|
static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
|
|
.get_head = pci_sun4v_get_head,
|
|
.dequeue_msi = pci_sun4v_dequeue_msi,
|
|
.set_head = pci_sun4v_set_head,
|
|
.msi_setup = pci_sun4v_msi_setup,
|
|
.msi_teardown = pci_sun4v_msi_teardown,
|
|
.msiq_alloc = pci_sun4v_msiq_alloc,
|
|
.msiq_free = pci_sun4v_msiq_free,
|
|
.msiq_build_irq = pci_sun4v_msiq_build_irq,
|
|
};
|
|
|
|
static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
|
|
{
|
|
sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
|
|
}
|
|
#else /* CONFIG_PCI_MSI */
|
|
static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
|
|
{
|
|
}
|
|
#endif /* !(CONFIG_PCI_MSI) */
|
|
|
|
static void __init pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
|
|
{
|
|
struct pci_pbm_info *pbm;
|
|
|
|
if (devhandle & 0x40)
|
|
pbm = &p->pbm_B;
|
|
else
|
|
pbm = &p->pbm_A;
|
|
|
|
pbm->next = pci_pbm_root;
|
|
pci_pbm_root = pbm;
|
|
|
|
pbm->scan_bus = pci_sun4v_scan_bus;
|
|
pbm->pci_ops = &sun4v_pci_ops;
|
|
pbm->config_space_reg_bits = 12;
|
|
|
|
pbm->index = pci_num_pbms++;
|
|
|
|
pbm->parent = p;
|
|
pbm->prom_node = dp;
|
|
|
|
pbm->devhandle = devhandle;
|
|
|
|
pbm->name = dp->full_name;
|
|
|
|
printk("%s: SUN4V PCI Bus Module\n", pbm->name);
|
|
|
|
pci_determine_mem_io_space(pbm);
|
|
|
|
pci_get_pbm_props(pbm);
|
|
pci_sun4v_iommu_init(pbm);
|
|
pci_sun4v_msi_init(pbm);
|
|
}
|
|
|
|
void __init sun4v_pci_init(struct device_node *dp, char *model_name)
|
|
{
|
|
static int hvapi_negotiated = 0;
|
|
struct pci_controller_info *p;
|
|
struct pci_pbm_info *pbm;
|
|
struct iommu *iommu;
|
|
struct property *prop;
|
|
struct linux_prom64_registers *regs;
|
|
u32 devhandle;
|
|
int i;
|
|
|
|
if (!hvapi_negotiated++) {
|
|
int err = sun4v_hvapi_register(HV_GRP_PCI,
|
|
vpci_major,
|
|
&vpci_minor);
|
|
|
|
if (err) {
|
|
prom_printf("SUN4V_PCI: Could not register hvapi, "
|
|
"err=%d\n", err);
|
|
prom_halt();
|
|
}
|
|
printk("SUN4V_PCI: Registered hvapi major[%lu] minor[%lu]\n",
|
|
vpci_major, vpci_minor);
|
|
|
|
dma_ops = &sun4v_dma_ops;
|
|
}
|
|
|
|
prop = of_find_property(dp, "reg", NULL);
|
|
regs = prop->value;
|
|
|
|
devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
|
|
|
|
for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
|
|
if (pbm->devhandle == (devhandle ^ 0x40)) {
|
|
pci_sun4v_pbm_init(pbm->parent, dp, devhandle);
|
|
return;
|
|
}
|
|
}
|
|
|
|
for_each_possible_cpu(i) {
|
|
unsigned long page = get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page)
|
|
goto fatal_memory_error;
|
|
|
|
per_cpu(iommu_batch, i).pglist = (u64 *) page;
|
|
}
|
|
|
|
p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
|
|
if (!p)
|
|
goto fatal_memory_error;
|
|
|
|
iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
|
|
if (!iommu)
|
|
goto fatal_memory_error;
|
|
|
|
p->pbm_A.iommu = iommu;
|
|
|
|
iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
|
|
if (!iommu)
|
|
goto fatal_memory_error;
|
|
|
|
p->pbm_B.iommu = iommu;
|
|
|
|
pci_sun4v_pbm_init(p, dp, devhandle);
|
|
return;
|
|
|
|
fatal_memory_error:
|
|
prom_printf("SUN4V_PCI: Fatal memory allocation error.\n");
|
|
prom_halt();
|
|
}
|