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Shared mailboxes are a mechanism to transport data from one processor in the system to another. They are bidirectional links with both a producer and a consumer. Interrupts are used to let the consumer know when data was written to the mailbox by the producer, and to let the producer know when the consumer has read the data from the mailbox. These interrupts are mapped to one or more "shared interrupts". Typically each processor in the system owns one of these shared interrupts. Add documentation to the device tree bindings about how clients can use mailbox specifiers to request a specific shared mailbox and select which direction they drive. Also document how to specify the shared interrupts in addition to the existing doorbell interrupt. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
73 lines
2.6 KiB
Plaintext
73 lines
2.6 KiB
Plaintext
NVIDIA Tegra Hardware Synchronization Primitives (HSP)
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The HSP modules are used for the processors to share resources and communicate
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together. It provides a set of hardware synchronization primitives for
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interprocessor communication. So the interprocessor communication (IPC)
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protocols can use hardware synchronization primitives, when operating between
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two processors not in an SMP relationship.
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The features that HSP supported are shared mailboxes, shared semaphores,
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arbitrated semaphores and doorbells.
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Required properties:
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- name : Should be hsp
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- compatible
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Array of strings.
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one of:
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- "nvidia,tegra186-hsp"
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- "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
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- reg : Offset and length of the register set for the device.
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- interrupt-names
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Array of strings.
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Contains a list of names for the interrupts described by the interrupt
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property. May contain the following entries, in any order:
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- "doorbell"
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- "sharedN", where 'N' is a number from zero up to the number of
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external interrupts supported by the HSP instance minus one.
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Users of this binding MUST look up entries in the interrupt property
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by name, using this interrupt-names property to do so.
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- interrupts
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Array of interrupt specifiers.
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Must contain one entry per entry in the interrupt-names property,
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in a matching order.
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- #mbox-cells : Should be 2.
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The mbox specifier of the "mboxes" property in the client node should contain
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two cells. The first cell determines the HSP type and the second cell is used
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to identify the mailbox that the client is going to use.
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For doorbells, the second cell specifies the index of the doorbell to use.
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For shared mailboxes, the second cell is composed of two fields:
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- bits 31..24:
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A bit mask of flags that further specify how the shared mailbox will be
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used. Valid flags are:
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- bit 31:
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Defines the direction of the mailbox. If set, the mailbox will be used
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as a producer (i.e. used to send data). If cleared, the mailbox is the
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consumer of data sent by a producer.
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- bits 23.. 0:
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The index of the shared mailbox to use. The number of available mailboxes
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may vary by instance of the HSP block and SoC generation.
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The following file contains definitions that can be used to construct mailbox
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specifiers:
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<dt-bindings/mailbox/tegra186-hsp.h>
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Example:
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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};
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client {
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...
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
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};
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