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1317824376
This patch is a painful merge of change
a90bab567ece3e915d0ccd55ab00c9bb333fa8c0 (viafb: Add support for 2D
accelerated framebuffer on VX800/VX855) in the OLPC tree, originally by
Harald Welte. Harald's changelog read:
The VX800/VX820 and the VX855/VX875 chipsets have a different 2D
acceleration engine called "M1". The M1 engine has some subtle
(and some not-so-subtle) differences to the previous engines, so
support for accelerated framebuffer on those chipsets was disabled
so far.
This merge tries to preserve Harald's changes in the framework of the
much-changed 2.6.34 viafb code.
Cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Cc: ScottFang@viatech.com.cn
Cc: JosephChan@via.com.tw
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
211 lines
7.5 KiB
C
211 lines
7.5 KiB
C
/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License as published by the Free Software Foundation;
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* either version 2, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
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* the implied warranty of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE.See the GNU General Public License
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* for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __ACCEL_H__
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#define __ACCEL_H__
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#define FB_ACCEL_VIA_UNICHROME 50
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/* MMIO Base Address Definition */
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#define MMIO_VGABASE 0x8000
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#define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
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#define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
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#define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
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#define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
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/* HW Cursor Status Define */
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#define HW_Cursor_ON 0
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#define HW_Cursor_OFF 1
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#define CURSOR_SIZE (8 * 1024)
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#define VQ_SIZE (256 * 1024)
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#define VIA_MMIO_BLTBASE 0x200000
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#define VIA_MMIO_BLTSIZE 0x200000
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/* Defines for 2D registers */
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#define VIA_REG_GECMD 0x000
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#define VIA_REG_GEMODE 0x004
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#define VIA_REG_SRCPOS 0x008
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#define VIA_REG_DSTPOS 0x00C
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/* width and height */
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#define VIA_REG_DIMENSION 0x010
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#define VIA_REG_PATADDR 0x014
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#define VIA_REG_FGCOLOR 0x018
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#define VIA_REG_BGCOLOR 0x01C
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/* top and left of clipping */
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#define VIA_REG_CLIPTL 0x020
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/* bottom and right of clipping */
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#define VIA_REG_CLIPBR 0x024
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#define VIA_REG_OFFSET 0x028
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/* color key control */
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#define VIA_REG_KEYCONTROL 0x02C
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#define VIA_REG_SRCBASE 0x030
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#define VIA_REG_DSTBASE 0x034
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/* pitch of src and dst */
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#define VIA_REG_PITCH 0x038
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#define VIA_REG_MONOPAT0 0x03C
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#define VIA_REG_MONOPAT1 0x040
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/* from 0x100 to 0x1ff */
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#define VIA_REG_COLORPAT 0x100
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/* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/
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#define VIA_REG_GECMD_M1 0x000
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#define VIA_REG_GEMODE_M1 0x004
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#define VIA_REG_GESTATUS_M1 0x004 /* as same as VIA_REG_GEMODE */
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#define VIA_REG_PITCH_M1 0x008 /* pitch of src and dst */
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#define VIA_REG_DIMENSION_M1 0x00C /* width and height */
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#define VIA_REG_DSTPOS_M1 0x010
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#define VIA_REG_LINE_XY_M1 0x010
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#define VIA_REG_DSTBASE_M1 0x014
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#define VIA_REG_SRCPOS_M1 0x018
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#define VIA_REG_LINE_K1K2_M1 0x018
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#define VIA_REG_SRCBASE_M1 0x01C
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#define VIA_REG_PATADDR_M1 0x020
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#define VIA_REG_MONOPAT0_M1 0x024
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#define VIA_REG_MONOPAT1_M1 0x028
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#define VIA_REG_OFFSET_M1 0x02C
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#define VIA_REG_LINE_ERROR_M1 0x02C
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#define VIA_REG_CLIPTL_M1 0x040 /* top and left of clipping */
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#define VIA_REG_CLIPBR_M1 0x044 /* bottom and right of clipping */
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#define VIA_REG_KEYCONTROL_M1 0x048 /* color key control */
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#define VIA_REG_FGCOLOR_M1 0x04C
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#define VIA_REG_DSTCOLORKEY_M1 0x04C /* as same as VIA_REG_FG */
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#define VIA_REG_BGCOLOR_M1 0x050
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#define VIA_REG_SRCCOLORKEY_M1 0x050 /* as same as VIA_REG_BG */
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#define VIA_REG_MONOPATFGC_M1 0x058 /* Add BG color of Pattern. */
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#define VIA_REG_MONOPATBGC_M1 0x05C /* Add FG color of Pattern. */
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#define VIA_REG_COLORPAT_M1 0x100 /* from 0x100 to 0x1ff */
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/* VIA_REG_PITCH(0x38): Pitch Setting */
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#define VIA_PITCH_ENABLE 0x80000000
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/* defines for VIA HW cursor registers */
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#define VIA_REG_CURSOR_MODE 0x2D0
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#define VIA_REG_CURSOR_POS 0x2D4
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#define VIA_REG_CURSOR_ORG 0x2D8
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#define VIA_REG_CURSOR_BG 0x2DC
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#define VIA_REG_CURSOR_FG 0x2E0
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/* VIA_REG_GEMODE(0x04): GE mode */
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#define VIA_GEM_8bpp 0x00000000
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#define VIA_GEM_16bpp 0x00000100
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#define VIA_GEM_32bpp 0x00000300
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/* VIA_REG_GECMD(0x00): 2D Engine Command */
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#define VIA_GEC_NOOP 0x00000000
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#define VIA_GEC_BLT 0x00000001
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#define VIA_GEC_LINE 0x00000005
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/* Rotate Command */
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#define VIA_GEC_ROT 0x00000008
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#define VIA_GEC_SRC_XY 0x00000000
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#define VIA_GEC_SRC_LINEAR 0x00000010
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#define VIA_GEC_DST_XY 0x00000000
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#define VIA_GEC_DST_LINRAT 0x00000020
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#define VIA_GEC_SRC_FB 0x00000000
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#define VIA_GEC_SRC_SYS 0x00000040
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#define VIA_GEC_DST_FB 0x00000000
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#define VIA_GEC_DST_SYS 0x00000080
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/* source is mono */
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#define VIA_GEC_SRC_MONO 0x00000100
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/* pattern is mono */
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#define VIA_GEC_PAT_MONO 0x00000200
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/* mono src is opaque */
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#define VIA_GEC_MSRC_OPAQUE 0x00000000
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/* mono src is transparent */
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#define VIA_GEC_MSRC_TRANS 0x00000400
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/* pattern is in frame buffer */
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#define VIA_GEC_PAT_FB 0x00000000
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/* pattern is from reg setting */
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#define VIA_GEC_PAT_REG 0x00000800
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#define VIA_GEC_CLIP_DISABLE 0x00000000
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#define VIA_GEC_CLIP_ENABLE 0x00001000
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#define VIA_GEC_FIXCOLOR_PAT 0x00002000
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#define VIA_GEC_INCX 0x00000000
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#define VIA_GEC_DECY 0x00004000
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#define VIA_GEC_INCY 0x00000000
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#define VIA_GEC_DECX 0x00008000
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/* mono pattern is opaque */
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#define VIA_GEC_MPAT_OPAQUE 0x00000000
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/* mono pattern is transparent */
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#define VIA_GEC_MPAT_TRANS 0x00010000
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#define VIA_GEC_MONO_UNPACK 0x00000000
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#define VIA_GEC_MONO_PACK 0x00020000
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#define VIA_GEC_MONO_DWORD 0x00000000
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#define VIA_GEC_MONO_WORD 0x00040000
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#define VIA_GEC_MONO_BYTE 0x00080000
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#define VIA_GEC_LASTPIXEL_ON 0x00000000
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#define VIA_GEC_LASTPIXEL_OFF 0x00100000
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#define VIA_GEC_X_MAJOR 0x00000000
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#define VIA_GEC_Y_MAJOR 0x00200000
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#define VIA_GEC_QUICK_START 0x00800000
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/* defines for VIA 3D registers */
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#define VIA_REG_STATUS 0x400
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#define VIA_REG_CR_TRANSET 0x41C
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#define VIA_REG_CR_TRANSPACE 0x420
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#define VIA_REG_TRANSET 0x43C
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#define VIA_REG_TRANSPACE 0x440
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/* VIA_REG_STATUS(0x400): Engine Status */
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/* Command Regulator is busy */
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#define VIA_CMD_RGTR_BUSY 0x00000080
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/* 2D Engine is busy */
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#define VIA_2D_ENG_BUSY 0x00000002
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/* 3D Engine is busy */
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#define VIA_3D_ENG_BUSY 0x00000001
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/* Virtual Queue is busy */
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#define VIA_VR_QUEUE_BUSY 0x00020000
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/* VIA_REG_STATUS(0x400): Engine Status for H5 */
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#define VIA_CMD_RGTR_BUSY_H5 0x00000010 /* Command Regulator is busy */
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#define VIA_2D_ENG_BUSY_H5 0x00000002 /* 2D Engine is busy */
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#define VIA_3D_ENG_BUSY_H5 0x00001FE1 /* 3D Engine is busy */
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#define VIA_VR_QUEUE_BUSY_H5 0x00000004 /* Virtual Queue is busy */
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/* VIA_REG_STATUS(0x400): Engine Status for VT3353/3409 */
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#define VIA_CMD_RGTR_BUSY_M1 0x00000010 /* Command Regulator is busy */
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#define VIA_2D_ENG_BUSY_M1 0x00000002 /* 2D Engine is busy */
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#define VIA_3D_ENG_BUSY_M1 0x00001FE1 /* 3D Engine is busy */
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#define VIA_VR_QUEUE_BUSY_M1 0x00000004 /* Virtual Queue is busy */
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#define MAXLOOP 0xFFFFFF
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#define VIA_BITBLT_COLOR 1
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#define VIA_BITBLT_MONO 2
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#define VIA_BITBLT_FILL 3
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int viafb_init_engine(struct fb_info *info);
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void viafb_show_hw_cursor(struct fb_info *info, int Status);
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void viafb_wait_engine_idle(struct fb_info *info);
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#endif /* __ACCEL_H__ */
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