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2bbba277a5
An implicit instance of module.h leaked back into existence and was masking the fact that these drivers weren't calling out the include for itself. Fix the drivers before we remove the implicit include path via net/netprio_cgroup.h file. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
551 lines
11 KiB
C
551 lines
11 KiB
C
/*
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* net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#include "mv88e6xxx.h"
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/*
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* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
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* use all 32 SMI bus addresses on its SMI bus, and all switch registers
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* will be directly accessible on some {device address,register address}
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* pair. If the ADDR[4:0] pins are not strapped to zero, the switch
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* will only respond to SMI transactions to that specific address, and
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* an indirect addressing mechanism needs to be used to access its
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* registers.
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*/
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static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
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{
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int ret;
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int i;
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for (i = 0; i < 16; i++) {
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ret = mdiobus_read(bus, sw_addr, 0);
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if (ret < 0)
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return ret;
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if ((ret & 0x8000) == 0)
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return 0;
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}
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return -ETIMEDOUT;
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}
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int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
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{
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int ret;
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if (sw_addr == 0)
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return mdiobus_read(bus, addr, reg);
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/*
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* Wait for the bus to become free.
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*/
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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/*
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* Transmit the read command.
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*/
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ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
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if (ret < 0)
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return ret;
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/*
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* Wait for the read command to complete.
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*/
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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/*
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* Read the data.
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*/
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ret = mdiobus_read(bus, sw_addr, 1);
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if (ret < 0)
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return ret;
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return ret & 0xffff;
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}
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int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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int ret;
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mutex_lock(&ps->smi_mutex);
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ret = __mv88e6xxx_reg_read(ds->master_mii_bus,
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ds->pd->sw_addr, addr, reg);
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mutex_unlock(&ps->smi_mutex);
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return ret;
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}
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int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
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int reg, u16 val)
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{
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int ret;
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if (sw_addr == 0)
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return mdiobus_write(bus, addr, reg, val);
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/*
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* Wait for the bus to become free.
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*/
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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/*
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* Transmit the data to write.
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*/
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ret = mdiobus_write(bus, sw_addr, 1, val);
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if (ret < 0)
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return ret;
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/*
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* Transmit the write command.
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*/
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ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
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if (ret < 0)
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return ret;
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/*
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* Wait for the write command to complete.
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*/
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ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
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if (ret < 0)
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return ret;
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return 0;
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}
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int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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int ret;
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mutex_lock(&ps->smi_mutex);
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ret = __mv88e6xxx_reg_write(ds->master_mii_bus,
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ds->pd->sw_addr, addr, reg, val);
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mutex_unlock(&ps->smi_mutex);
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return ret;
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}
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int mv88e6xxx_config_prio(struct dsa_switch *ds)
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{
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/*
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* Configure the IP ToS mapping registers.
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*/
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REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
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REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
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REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
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REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
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REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
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REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
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REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
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REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
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/*
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* Configure the IEEE 802.1p priority mapping register.
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*/
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REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
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return 0;
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}
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int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
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{
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REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
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REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
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REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
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return 0;
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}
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int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
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{
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int i;
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int ret;
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for (i = 0; i < 6; i++) {
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int j;
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/*
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* Write the MAC address byte.
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*/
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REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
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/*
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* Wait for the write to complete.
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*/
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for (j = 0; j < 16; j++) {
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ret = REG_READ(REG_GLOBAL2, 0x0d);
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if ((ret & 0x8000) == 0)
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break;
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}
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if (j == 16)
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return -ETIMEDOUT;
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}
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return 0;
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}
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int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
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{
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if (addr >= 0)
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return mv88e6xxx_reg_read(ds, addr, regnum);
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return 0xffff;
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}
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int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
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{
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if (addr >= 0)
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return mv88e6xxx_reg_write(ds, addr, regnum, val);
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return 0;
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}
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#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
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static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
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{
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int ret;
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int i;
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ret = REG_READ(REG_GLOBAL, 0x04);
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REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
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for (i = 0; i < 1000; i++) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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msleep(1);
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if ((ret & 0xc000) != 0xc000)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
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{
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int ret;
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int i;
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ret = REG_READ(REG_GLOBAL, 0x04);
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REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
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for (i = 0; i < 1000; i++) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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msleep(1);
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if ((ret & 0xc000) == 0xc000)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
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{
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struct mv88e6xxx_priv_state *ps;
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ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
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if (mutex_trylock(&ps->ppu_mutex)) {
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struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
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if (mv88e6xxx_ppu_enable(ds) == 0)
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ps->ppu_disabled = 0;
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mutex_unlock(&ps->ppu_mutex);
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}
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}
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static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
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{
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struct mv88e6xxx_priv_state *ps = (void *)_ps;
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schedule_work(&ps->ppu_work);
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}
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static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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int ret;
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mutex_lock(&ps->ppu_mutex);
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/*
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* If the PHY polling unit is enabled, disable it so that
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* we can access the PHY registers. If it was already
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* disabled, cancel the timer that is going to re-enable
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* it.
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*/
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if (!ps->ppu_disabled) {
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ret = mv88e6xxx_ppu_disable(ds);
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if (ret < 0) {
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mutex_unlock(&ps->ppu_mutex);
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return ret;
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}
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ps->ppu_disabled = 1;
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} else {
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del_timer(&ps->ppu_timer);
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ret = 0;
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}
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return ret;
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}
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static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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/*
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* Schedule a timer to re-enable the PHY polling unit.
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*/
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mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
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mutex_unlock(&ps->ppu_mutex);
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}
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void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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mutex_init(&ps->ppu_mutex);
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INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
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init_timer(&ps->ppu_timer);
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ps->ppu_timer.data = (unsigned long)ps;
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ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
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}
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int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
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{
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int ret;
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ret = mv88e6xxx_ppu_access_get(ds);
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if (ret >= 0) {
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ret = mv88e6xxx_reg_read(ds, addr, regnum);
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mv88e6xxx_ppu_access_put(ds);
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}
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return ret;
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}
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int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
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int regnum, u16 val)
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{
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int ret;
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ret = mv88e6xxx_ppu_access_get(ds);
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if (ret >= 0) {
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ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
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mv88e6xxx_ppu_access_put(ds);
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}
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return ret;
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}
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#endif
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void mv88e6xxx_poll_link(struct dsa_switch *ds)
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{
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int i;
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for (i = 0; i < DSA_MAX_PORTS; i++) {
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struct net_device *dev;
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int uninitialized_var(port_status);
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int link;
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int speed;
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int duplex;
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int fc;
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dev = ds->ports[i];
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if (dev == NULL)
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continue;
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link = 0;
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if (dev->flags & IFF_UP) {
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port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
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if (port_status < 0)
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continue;
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link = !!(port_status & 0x0800);
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}
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if (!link) {
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if (netif_carrier_ok(dev)) {
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printk(KERN_INFO "%s: link down\n", dev->name);
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netif_carrier_off(dev);
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}
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continue;
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}
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switch (port_status & 0x0300) {
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case 0x0000:
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speed = 10;
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break;
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case 0x0100:
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speed = 100;
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break;
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case 0x0200:
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speed = 1000;
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break;
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default:
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speed = -1;
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break;
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}
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duplex = (port_status & 0x0400) ? 1 : 0;
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fc = (port_status & 0x8000) ? 1 : 0;
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if (!netif_carrier_ok(dev)) {
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printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
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"flow control %sabled\n", dev->name,
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speed, duplex ? "full" : "half",
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fc ? "en" : "dis");
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netif_carrier_on(dev);
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}
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}
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}
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static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
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{
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int ret;
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int i;
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for (i = 0; i < 10; i++) {
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ret = REG_READ(REG_GLOBAL, 0x1d);
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if ((ret & 0x8000) == 0)
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return 0;
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}
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return -ETIMEDOUT;
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}
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static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
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{
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int ret;
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/*
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* Snapshot the hardware statistics counters for this port.
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*/
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REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
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/*
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* Wait for the snapshotting to complete.
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*/
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ret = mv88e6xxx_stats_wait(ds);
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if (ret < 0)
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return ret;
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return 0;
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}
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static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
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{
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u32 _val;
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int ret;
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*val = 0;
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ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
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if (ret < 0)
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return;
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ret = mv88e6xxx_stats_wait(ds);
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if (ret < 0)
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return;
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
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if (ret < 0)
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return;
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_val = ret << 16;
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ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
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if (ret < 0)
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return;
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*val = _val | ret;
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}
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void mv88e6xxx_get_strings(struct dsa_switch *ds,
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int nr_stats, struct mv88e6xxx_hw_stat *stats,
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int port, uint8_t *data)
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{
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int i;
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for (i = 0; i < nr_stats; i++) {
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memcpy(data + i * ETH_GSTRING_LEN,
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stats[i].string, ETH_GSTRING_LEN);
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}
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}
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void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
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int nr_stats, struct mv88e6xxx_hw_stat *stats,
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int port, uint64_t *data)
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{
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struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
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int ret;
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int i;
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mutex_lock(&ps->stats_mutex);
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ret = mv88e6xxx_stats_snapshot(ds, port);
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if (ret < 0) {
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mutex_unlock(&ps->stats_mutex);
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return;
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}
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/*
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* Read each of the counters.
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*/
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for (i = 0; i < nr_stats; i++) {
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struct mv88e6xxx_hw_stat *s = stats + i;
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u32 low;
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u32 high;
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mv88e6xxx_stats_read(ds, s->reg, &low);
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if (s->sizeof_stat == 8)
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mv88e6xxx_stats_read(ds, s->reg + 1, &high);
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else
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high = 0;
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data[i] = (((u64)high) << 32) | low;
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}
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mutex_unlock(&ps->stats_mutex);
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}
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static int __init mv88e6xxx_init(void)
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{
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#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
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register_switch_driver(&mv88e6131_switch_driver);
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#endif
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#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
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register_switch_driver(&mv88e6123_61_65_switch_driver);
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#endif
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return 0;
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}
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module_init(mv88e6xxx_init);
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static void __exit mv88e6xxx_cleanup(void)
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{
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#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
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unregister_switch_driver(&mv88e6123_61_65_switch_driver);
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#endif
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#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
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unregister_switch_driver(&mv88e6131_switch_driver);
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#endif
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}
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module_exit(mv88e6xxx_cleanup);
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MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
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MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
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MODULE_LICENSE("GPL");
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