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a5f40e8098
Many PCI host controller drivers aren't prepared to have their devices unbound from them forcefully (e.g., through /sys/.../<driver>/unbind), as they don't provide any driver .remove callback, where they'd detach the root bus, release resources, etc. Keeping the driver built in (i.e., not a loadable module) is not enough; and providing no .remove callback just means we don't do any teardown. To rule out the possibility of unbinding a device via sysfs, we need to set the ".suppress_bind_attrs" field. I found the suspect drivers via the following search: git grep -l platform_driver $(git grep -L -e '\.remove' -e suppress_bind_attrs drivers/pci/) Then I inspected them to ensure that (a) they set up a PCI bus in their probe() and (b) they don't have a remove() callback for undoing the setup Suggested-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
384 lines
9.6 KiB
C
384 lines
9.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2015, 2016 Cavium, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/of_pci.h>
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#include <linux/of.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
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static void set_val(u32 v, int where, int size, u32 *val)
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{
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int shift = (where & 3) * 8;
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pr_debug("set_val %04x: %08x\n", (unsigned)(where & ~3), v);
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v >>= shift;
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if (size == 1)
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v &= 0xff;
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else if (size == 2)
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v &= 0xffff;
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*val = v;
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}
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static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val)
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{
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void __iomem *addr;
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u32 v;
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/* Entries are 16-byte aligned; bits[2,3] select word in entry */
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int where_a = where & 0xc;
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if (where_a == 0) {
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set_val(e0, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0x4) {
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addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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v &= ~0xf;
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v |= 2; /* EA entry-1. Base-L */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0x8) {
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u32 barl_orig;
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u32 barl_rb;
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addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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barl_orig = readl(addr + 0);
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writel(0xffffffff, addr + 0);
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barl_rb = readl(addr + 0);
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writel(barl_orig, addr + 0);
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/* zeros in unsettable bits */
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v = ~barl_rb & ~3;
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v |= 0xc; /* EA entry-2. Offset-L */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc) {
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addr = bus->ops->map_bus(bus, devfn, bar + 4); /* BAR 1 */
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr); /* EA entry-3. Base-H */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static int thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct pci_config_window *cfg = bus->sysdata;
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int where_a = where & ~3;
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void __iomem *addr;
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u32 node_bits;
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u32 v;
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/* EA Base[63:32] may be missing some bits ... */
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switch (where_a) {
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case 0xa8:
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case 0xbc:
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case 0xd0:
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case 0xe4:
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break;
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default:
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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addr = bus->ops->map_bus(bus, devfn, where_a);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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/*
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* Bit 44 of the 64-bit Base must match the same bit in
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* the config space access window. Since we are working with
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* the high-order 32 bits, shift everything down by 32 bits.
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*/
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node_bits = (cfg->res.start >> 32) & (1 << 12);
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v |= node_bits;
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 v;
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u32 vendor_device;
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u32 class_rev;
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void __iomem *addr;
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int cfg_type;
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int where_a = where & ~3;
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addr = bus->ops->map_bus(bus, devfn, 0xc);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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/* Check for non type-00 header */
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cfg_type = (v >> 16) & 0x7f;
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addr = bus->ops->map_bus(bus, devfn, 8);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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class_rev = readl(addr);
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if (class_rev == 0xffffffff)
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goto no_emulation;
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if ((class_rev & 0xff) >= 8) {
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/* Pass-2 handling */
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if (cfg_type)
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goto no_emulation;
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return thunder_ecam_p2_config_read(bus, devfn, where,
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size, val);
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}
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/*
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* All BARs have fixed addresses specified by the EA
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* capability; they must return zero on read.
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*/
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if (cfg_type == 0 &&
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((where >= 0x10 && where < 0x2c) ||
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(where >= 0x1a4 && where < 0x1bc))) {
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/* BAR or SR-IOV BAR */
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*val = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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addr = bus->ops->map_bus(bus, devfn, 0);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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vendor_device = readl(addr);
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if (vendor_device == 0xffffffff)
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goto no_emulation;
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pr_debug("%04x:%04x - Fix pass#: %08x, where: %03x, devfn: %03x\n",
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vendor_device & 0xffff, vendor_device >> 16, class_rev,
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(unsigned) where, devfn);
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/* Check for non type-00 header */
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if (cfg_type == 0) {
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bool has_msix;
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bool is_nic = (vendor_device == 0xa01e177d);
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bool is_tns = (vendor_device == 0xa01f177d);
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addr = bus->ops->map_bus(bus, devfn, 0x70);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/* E_CAP */
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v = readl(addr);
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has_msix = (v & 0xff00) != 0;
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if (!has_msix && where_a == 0x70) {
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v |= 0xbc00; /* next capability is EA at 0xbc */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xb0) {
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addr = bus->ops->map_bus(bus, devfn, where_a);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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if (v & 0xff00)
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pr_err("Bad MSIX cap header: %08x\n", v);
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v |= 0xbc00; /* next capability is EA at 0xbc */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xbc) {
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if (is_nic)
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v = 0x40014; /* EA last in chain, 4 entries */
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else if (is_tns)
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v = 0x30014; /* EA last in chain, 3 entries */
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else if (has_msix)
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v = 0x20014; /* EA last in chain, 2 entries */
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else
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v = 0x10014; /* EA last in chain, 1 entry */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a >= 0xc0 && where_a < 0xd0)
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/* EA entry-0. PP=0, BAR0 Size:3 */
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return handle_ea_bar(0x80ff0003,
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0x10, bus, devfn, where,
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size, val);
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if (where_a >= 0xd0 && where_a < 0xe0 && has_msix)
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/* EA entry-1. PP=0, BAR4 Size:3 */
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return handle_ea_bar(0x80ff0043,
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0x20, bus, devfn, where,
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size, val);
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if (where_a >= 0xe0 && where_a < 0xf0 && is_tns)
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/* EA entry-2. PP=0, BAR2, Size:3 */
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return handle_ea_bar(0x80ff0023,
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0x18, bus, devfn, where,
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size, val);
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if (where_a >= 0xe0 && where_a < 0xf0 && is_nic)
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/* EA entry-2. PP=4, VF_BAR0 (9), Size:3 */
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return handle_ea_bar(0x80ff0493,
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0x1a4, bus, devfn, where,
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size, val);
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if (where_a >= 0xf0 && where_a < 0x100 && is_nic)
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/* EA entry-3. PP=4, VF_BAR4 (d), Size:3 */
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return handle_ea_bar(0x80ff04d3,
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0x1b4, bus, devfn, where,
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size, val);
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} else if (cfg_type == 1) {
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bool is_rsl_bridge = devfn == 0x08;
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bool is_rad_bridge = devfn == 0xa0;
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bool is_zip_bridge = devfn == 0xa8;
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bool is_dfa_bridge = devfn == 0xb0;
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bool is_nic_bridge = devfn == 0x10;
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if (where_a == 0x70) {
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addr = bus->ops->map_bus(bus, devfn, where_a);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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if (v & 0xff00)
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pr_err("Bad PCIe cap header: %08x\n", v);
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v |= 0xbc00; /* next capability is EA at 0xbc */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xbc) {
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if (is_nic_bridge)
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v = 0x10014; /* EA last in chain, 1 entry */
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else
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v = 0x00014; /* EA last in chain, no entries */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc0) {
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if (is_rsl_bridge || is_nic_bridge)
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v = 0x0101; /* subordinate:secondary = 1:1 */
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else if (is_rad_bridge)
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v = 0x0202; /* subordinate:secondary = 2:2 */
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else if (is_zip_bridge)
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v = 0x0303; /* subordinate:secondary = 3:3 */
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else if (is_dfa_bridge)
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v = 0x0404; /* subordinate:secondary = 4:4 */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc4 && is_nic_bridge) {
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/* Enabled, not-Write, SP=ff, PP=05, BEI=6, ES=4 */
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v = 0x80ff0564;
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc8 && is_nic_bridge) {
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v = 0x00000002; /* Base-L 64-bit */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xcc && is_nic_bridge) {
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v = 0xfffffffe; /* MaxOffset-L 64-bit */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xd0 && is_nic_bridge) {
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v = 0x00008430; /* NIC Base-H */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xd4 && is_nic_bridge) {
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v = 0x0000000f; /* MaxOffset-H */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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}
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no_emulation:
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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/*
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* All BARs have fixed addresses; ignore BAR writes so they
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* don't get corrupted.
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*/
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if ((where >= 0x10 && where < 0x2c) ||
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(where >= 0x1a4 && where < 0x1bc))
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/* BAR or SR-IOV BAR */
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return PCIBIOS_SUCCESSFUL;
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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struct pci_ecam_ops pci_thunder_ecam_ops = {
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.bus_shift = 20,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = thunder_ecam_config_read,
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.write = thunder_ecam_config_write,
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}
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};
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#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
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static const struct of_device_id thunder_ecam_of_match[] = {
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{ .compatible = "cavium,pci-host-thunder-ecam" },
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{ },
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};
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static int thunder_ecam_probe(struct platform_device *pdev)
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{
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return pci_host_common_probe(pdev, &pci_thunder_ecam_ops);
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}
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static struct platform_driver thunder_ecam_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = thunder_ecam_of_match,
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.suppress_bind_attrs = true,
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},
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.probe = thunder_ecam_probe,
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};
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builtin_platform_driver(thunder_ecam_driver);
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#endif
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#endif
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