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81d7cac4d1
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> [mpe: Fixup maple/setup.c which needs platform_device] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230724210247.778034-1-robh@kernel.org
269 lines
6.8 KiB
C
269 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Board setup routines for the IBM 750GX/CL platform w/ TSI10x bridge
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*
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* Copyright 2007 IBM Corporation
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*
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* Stephen Winiecki <stevewin@us.ibm.com>
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* Josh Boyer <jwboyer@linux.vnet.ibm.com>
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*
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* Based on code from mpc7448_hpc2.c
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/serial_core.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/extable.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/udbg.h>
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#include <asm/tsi108.h>
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#include <asm/pci-bridge.h>
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#include <asm/reg.h>
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#include <mm/mmu_decl.h>
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#include <asm/tsi108_irq.h>
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#include <asm/tsi108_pci.h>
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#include <asm/mpic.h>
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#undef DEBUG
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#define HOLLY_PCI_CFG_PHYS 0x7c000000
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static int holly_exclude_device(struct pci_controller *hose, u_char bus,
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u_char devfn)
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{
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if (bus == 0 && PCI_SLOT(devfn) == 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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else
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return PCIBIOS_SUCCESSFUL;
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}
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static void __init holly_remap_bridge(void)
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{
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u32 lut_val, lut_addr;
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int i;
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printk(KERN_INFO "Remapping PCI bridge\n");
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/* Re-init the PCI bridge and LUT registers to have mappings that don't
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* rely on PIBS
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*/
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lut_addr = 0x900;
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for (i = 0; i < 31; i++) {
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tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000201);
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lut_addr += 4;
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tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0);
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lut_addr += 4;
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}
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/* Reserve the last LUT entry for PCI I/O space */
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tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000241);
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lut_addr += 4;
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tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0);
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/* Map PCI I/O space */
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tsi108_write_reg(TSI108_PCI_PFAB_IO_UPPER, 0x0);
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tsi108_write_reg(TSI108_PCI_PFAB_IO, 0x1);
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/* Map PCI CFG space */
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tsi108_write_reg(TSI108_PCI_PFAB_BAR0_UPPER, 0x0);
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tsi108_write_reg(TSI108_PCI_PFAB_BAR0, 0x7c000000 | 0x01);
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/* We don't need MEM32 and PRM remapping so disable them */
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tsi108_write_reg(TSI108_PCI_PFAB_MEM32, 0x0);
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tsi108_write_reg(TSI108_PCI_PFAB_PFM3, 0x0);
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tsi108_write_reg(TSI108_PCI_PFAB_PFM4, 0x0);
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/* Set P2O_BAR0 */
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tsi108_write_reg(TSI108_PCI_P2O_BAR0_UPPER, 0x0);
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tsi108_write_reg(TSI108_PCI_P2O_BAR0, 0xc0000000);
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/* Init the PCI LUTs to do no remapping */
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lut_addr = 0x500;
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lut_val = 0x00000002;
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for (i = 0; i < 32; i++) {
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tsi108_write_reg(TSI108_PCI_OFFSET + lut_addr, lut_val);
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lut_addr += 4;
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tsi108_write_reg(TSI108_PCI_OFFSET + lut_addr, 0x40000000);
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lut_addr += 4;
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lut_val += 0x02000000;
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}
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tsi108_write_reg(TSI108_PCI_P2O_PAGE_SIZES, 0x00007900);
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/* Set 64-bit PCI bus address for system memory */
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tsi108_write_reg(TSI108_PCI_P2O_BAR2_UPPER, 0x0);
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tsi108_write_reg(TSI108_PCI_P2O_BAR2, 0x0);
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}
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static void __init holly_init_pci(void)
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{
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struct device_node *np;
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if (ppc_md.progress)
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ppc_md.progress("holly_setup_arch():set_bridge", 0);
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/* setup PCI host bridge */
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holly_remap_bridge();
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np = of_find_node_by_type(NULL, "pci");
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if (np)
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tsi108_setup_pci(np, HOLLY_PCI_CFG_PHYS, 1);
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of_node_put(np);
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ppc_md.pci_exclude_device = holly_exclude_device;
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if (ppc_md.progress)
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ppc_md.progress("tsi108: resources set", 0x100);
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}
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static void __init holly_setup_arch(void)
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{
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tsi108_csr_vir_base = get_vir_csrbase();
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printk(KERN_INFO "PPC750GX/CL Platform\n");
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}
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/*
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* Interrupt setup and service. Interrupts on the holly come
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* from the four external INT pins, PCI interrupts are routed via
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* PCI interrupt control registers, it generates internal IRQ23
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*
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* Interrupt routing on the Holly Board:
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* TSI108:PB_INT[0] -> CPU0:INT#
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* TSI108:PB_INT[1] -> CPU0:MCP#
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* TSI108:PB_INT[2] -> N/C
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* TSI108:PB_INT[3] -> N/C
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*/
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static void __init holly_init_IRQ(void)
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{
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struct mpic *mpic;
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#ifdef CONFIG_PCI
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unsigned int cascade_pci_irq;
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struct device_node *tsi_pci;
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struct device_node *cascade_node = NULL;
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#endif
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mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
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MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
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24, 0,
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"Tsi108_PIC");
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BUG_ON(mpic == NULL);
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mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
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mpic_init(mpic);
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#ifdef CONFIG_PCI
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tsi_pci = of_find_node_by_type(NULL, "pci");
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if (tsi_pci == NULL) {
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printk(KERN_ERR "%s: No tsi108 pci node found !\n", __func__);
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return;
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}
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cascade_node = of_find_node_by_type(NULL, "pic-router");
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if (cascade_node == NULL) {
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printk(KERN_ERR "%s: No tsi108 pci cascade node found !\n", __func__);
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return;
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}
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cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
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pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq);
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tsi108_pci_int_init(cascade_node);
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irq_set_handler_data(cascade_pci_irq, mpic);
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irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
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of_node_put(tsi_pci);
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of_node_put(cascade_node);
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#endif
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/* Configure MPIC outputs to CPU0 */
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tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
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}
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static void holly_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: IBM\n");
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seq_printf(m, "machine\t\t: PPC750 GX/CL\n");
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}
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static void __noreturn holly_restart(char *cmd)
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{
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__be32 __iomem *ocn_bar1 = NULL;
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unsigned long bar;
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struct device_node *bridge = NULL;
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struct resource res;
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phys_addr_t addr = 0xc0000000;
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local_irq_disable();
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bridge = of_find_node_by_type(NULL, "tsi-bridge");
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if (bridge) {
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of_address_to_resource(bridge, 0, &res);
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addr = res.start;
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of_node_put(bridge);
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}
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addr += (TSI108_PB_OFFSET + 0x414);
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ocn_bar1 = ioremap(addr, 0x4);
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/* Turn on the BOOT bit so the addresses are correctly
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* routed to the HLP interface */
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bar = ioread32be(ocn_bar1);
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bar |= 2;
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iowrite32be(bar, ocn_bar1);
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iosync();
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/* Set SRR0 to the reset vector and turn on MSR_IP */
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mtspr(SPRN_SRR0, 0xfff00100);
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mtspr(SPRN_SRR1, MSR_IP);
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/* Do an rfi to jump back to firmware. Somewhat evil,
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* but it works
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*/
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__asm__ __volatile__("rfi" : : : "memory");
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/* Spin until reset happens. Shouldn't really get here */
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for (;;) ;
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}
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static int ppc750_machine_check_exception(struct pt_regs *regs)
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{
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const struct exception_table_entry *entry;
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/* Are we prepared to handle this fault */
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if ((entry = search_exception_tables(regs->nip)) != NULL) {
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tsi108_clear_pci_cfg_error();
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regs_set_recoverable(regs);
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regs_set_return_ip(regs, extable_fixup(entry));
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return 1;
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}
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return 0;
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}
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define_machine(holly){
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.name = "PPC750 GX/CL TSI",
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.compatible = "ibm,holly",
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.setup_arch = holly_setup_arch,
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.discover_phbs = holly_init_pci,
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.init_IRQ = holly_init_IRQ,
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.show_cpuinfo = holly_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.restart = holly_restart,
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.machine_check_exception = ppc750_machine_check_exception,
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.progress = udbg_progress,
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};
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